Apparatus with embedded fine line space in a cavity, and a method for forming the same

Abstract

An apparatus is provided which comprises: a cavity made in a substrate of a printed circuit board (PCB); a plurality of solder balls embedded in the cavity; and a horizontal trace within the substrate, wherein the horizontal trace is partially directly under the plurality of solder balls and is coupled to the plurality of solder balls and another trace or via in the substrate such that a substrate region under the plurality of solder balls is independent of a stop layer under the cavity.

We claim: 
     
         1 . An integrated circuit (IC) die package comprising:
 a first layer of routing features on a first side of the IC die package, wherein the first layer of routing features is embedded within dielectric material and is adjacent to a cavity extending into the dielectric material from the first side;   a second layer of routing features embedded within dielectric material, wherein the second layer of routing features comprise routing features along a bottom surface of the cavity; and   a via embedded within dielectric material, wherein the via electrically couples the second layer of routing features to the first layer of routing features or to a third layer of routing features on a second side of the IC die package, opposite the first side.   
     
     
         2 . The IC die package of  claim 1 , wherein the routing features along the bottom surface of the cavity are substantially coplanar with dielectric material at the bottom surface of the cavity and adjacent to a sidewall of the routing features. 
     
     
         3 . The IC die package of  claim 1 , wherein the routing features along the bottom surface of the cavity comprise a horizontal trace that extends beyond a sidewall of the cavity. 
     
     
         4 . The IC die package of  claim 3 , wherein the horizontal trace is in contact with the via. 
     
     
         5 . The IC die package of  claim 1 , wherein at least one of the routing features along the bottom surface of the cavity is in contact with a second via that is further coupled to the third layer of routing features. 
     
     
         6 . The IC die package of  claim 5 , wherein the second via has a tapered sidewall profile with a wider end of the second via proximal to the third layer of routing features and a narrower end of the second via proximal to the routing features along the bottom surface of the cavity. 
     
     
         7 . The IC die package of  claim 1 , wherein the via electrically couples the second layer of routing features to the first layer of routing features, and wherein the via has a tapered sidewall profile with a wider end of the via proximal to the second layer of routing features and a narrower end of the via proximal to the first layer of routing features. 
     
     
         8 . The IC die package of  claim 1 , wherein the via electrically couples the second layer of routing features to the third layer of routing features, and wherein the via has a tapered sidewall profile with a narrower end of the via proximal to the second layer of routing features and a wider end of the via proximal to the third layer of routing features. 
     
     
         9 . The IC die package of  claim 1 , further comprising a plurality of solder features within the cavity, wherein individual ones of the solder features are coupled with individual ones of the routing features along the bottom surface of the cavity. 
     
     
         10 . The IC die package of  claim 9 , further comprising an IC die or a patch comprising high density routing within the cavity and electrically coupled to the solder features. 
     
     
         11 . An IC die package assembly, comprising:
 an IC die attached with solder to routing features on a bottom surface of a cavity extending into a package substrate from a first side;   a first layer of routing features embedded within the package substrate and adjacent to the cavity   a via embedded within the package substrate, wherein the via electrically couples routing features on the bottom surface of the cavity to at least one of the first layer of routing features or a second layer of routing features coupled to a second side of the package substrate, opposite the first side; and   a fill dielectric within a gap between the IC die and a sidewall of the cavity.   
     
     
         12 . The IC die package assembly of  claim 11 , wherein the fill dielectric is between features of the solder and in contact with dielectric material on the bottom surface of the cavity that is substantially coplanar with the routing features on the bottom surface of a cavity. 
     
     
         13 . The IC die package assembly of  claim 11 , wherein the via electrically couples the routing features on the bottom surface of the cavity to the first layer of routing features, and wherein the via has a tapered sidewall profile with a narrower end of the via proximal to the first layer of routing features. 
     
     
         14 . The IC die package assembly of  claim 11 , wherein the via electrically couples the routing features on the bottom surface of the cavity to the second layer of routing features, and wherein the via has a tapered sidewall profile with a wider end of the via proximal to the second layer of routing features. 
     
     
         15 . The IC die package assembly of  claim 11 , wherein the routing features along the bottom surface of the cavity comprise a horizontal trace that extends beyond a sidewall of the cavity and contacts the via. 
     
     
         16 . The IC die package assembly of  claim 11 , wherein the IC die comprises a processor with circuitry to execute instructions. 
     
     
         17 . The IC die package assembly of  claim 11 , wherein the second side of the package substrate comprises an interconnect interface to couple the second level of routing features with a host component. 
     
     
         18 . An IC die package assembly, comprising:
 a package comprising a cavity extending into the package from a first side;   an IC die attached with solder to package routing features on a bottom surface of the cavity, wherein the routing features comprise a horizontal trace that extends beyond a sidewall of the cavity;   a fill dielectric within a gap between the IC die and the sidewall of the cavity;   a first layer of routing features embedded within the package and adjacent to the cavity;   a second layer of routing features coupled to a second side of the package, opposite the first side; and   a via embedded within the package, wherein the via is in contact with the horizontal trace and is in contact with at least one of the first layer of routing features or the second layer of routing features.   
     
     
         19 . The IC die package assembly of  claim 18 , wherein the via electrically couples the horizontal trace to the first layer of routing features, and wherein the via has a tapered sidewall profile with a narrower end of the via proximal to the first layer of routing features. 
     
     
         20 . The IC die package assembly of  claim 18 , wherein the via electrically couples the horizontal trace to the second layer of routing features, and wherein the via has a tapered sidewall profile with a wider end of the via proximal to the second layer of routing features.