Semiconductor device having nanosheet transistor and methods of fabrication thereof

Abstract

Embodiments relate to a semiconductor device structure including a first channel layer having a first surface and a second surface, a second channel layer having a first surface and a second surface, and the first and second channel layers are formed of a first material. The structure also includes a first dopant suppression layer in contact with the second surface of the first channel layer, and a second dopant suppression layer parallel to the first dopant suppression layer. The second dopant suppression layer is in contact with the first surface of the second channel layer, and the first and second dopant suppression layers each comprises carbon or fluorine. The structure further includes a gate dielectric layer in contact with the first and second dopant suppression layers and the first surface of the first channel layer, and a gate electrode layer disposed on the gate dielectric layer.

1 . A semiconductor device structure, comprising:
 a first channel layer having a first surface and a second surface opposing the first surface, the first channel layer being formed of a first material;   a second channel layer having a first surface and a second surface opposing the first surface of the second channel layer, the second channel layer being formed of the first material;   a first dopant suppression layer in contact with the second surface of the first channel layer;   a second dopant suppression layer parallel to the first dopant suppression layer, the second dopant suppression layer being in contact with the first surface of the second channel layer, wherein the first and second dopant suppression layers each comprises carbon or fluorine;   a gate dielectric layer in contact with the first dopant suppression layer, the second dopant suppression layer, and the first surface of the first channel layer; and   a gate electrode layer disposed on the gate dielectric layer.   
     
     
         2 . The semiconductor device structure of  claim 1 , wherein each of the first dopant suppression layer and the second dopant suppression layer further comprises silicon, arsenic, or a combination thereof. 
     
     
         3 . The semiconductor device structure of  claim 2 , wherein the first dopant suppression layer and the second dopant suppression layer are silicon carbide, carbon doped silicon, or arsenic doped silicon carbide. 
     
     
         4 . The semiconductor device structure of  claim 1 , further comprising:
 a first source/drain feature in contact with the first dopant suppression layer and the second dopant suppression layer; and   a second source/drain feature in contact with the first dopant suppression layer and the second dopant suppression layer.   
     
     
         5 . The semiconductor device structure of  claim 1 , further comprising:
 a third dopant suppression layer in contact with a third surface of the first channel layer, the third surface connecting the first surface to the second surface of the first channel layer; and   a fourth dopant suppression layer in contact with a fourth surface of the first channel, the fourth surface opposing the third surface, and the fourth surface connecting the first surface to the second surface of the first channel layer.   
     
     
         6 . The semiconductor device structure of  claim 5 , wherein the third and fourth dopant suppression layers are formed of the same material as the first dopant suppression layer. 
     
     
         7 . The semiconductor device structure of  claim 5 , wherein the third and fourth dopant suppression layers are in contact with the first dopant suppression layer. 
     
     
         8 . The semiconductor device structure of  claim 5 , further comprising:
 a first source/drain feature in contact with the third dopant suppression layer; and   a second source/drain feature in contact with the fourth dopant suppression layer.   
     
     
         9 . The semiconductor device structure of  claim 8 , further comprising:
 a fifth dopant suppression layer in contact with the second surface of the second channel layer.   
     
     
         10 . The semiconductor device structure of  claim 9 , further comprising:
 a sixth dopant suppression layer disposed between and in contact with the second channel layer and the first source/drain feature; and   a seventh dopant suppression layer disposed between and in contact with the second channel layer and the second source/drain feature,   wherein the sixth and seventh dopant suppression layers are formed of the same material as the third and fourth dopant suppression layers.   
     
     
         11 . The semiconductor device structure of  claim 10 , wherein the second dopant suppression layer, the fifth dopant suppression layer, the sixth dopant suppression layer, and the seventh dopant suppression layer surround and in contact with the second channel layer. 
     
     
         12 . A semiconductor device structure, comprising:
 a first channel layer formed of a first material, the first channel layer comprising a first portion and a second portion, wherein the first portion has a first surface, a second surface opposing the first surface, a third surface, and a fourth surface opposing the third surface, the first surface connecting the third surface to the fourth surface, and the second surface connecting the third surface to the fourth surface, and wherein the second portion has a first surface, a second surface opposing the first surface of the second portion, a third surface, and a fourth surface opposing the third surface of the second portion, wherein the first surface of the second portion connecting the third surface to the fourth surface of the second portion, and the second surface of the second portion connecting the third surface to the fourth surface of the second portion;   a dopant suppression layer, comprising:
 a first part in contact with the second surface of the first portion and the first surface of the second portion; 
 a second part connecting to the first part and in contact with the third surface of the first portion and the third surface of the second portion; and 
 a third part connecting to the first part and in contact with the fourth surface of the first portion and the fourth surface of the second portion, wherein the first part, the second part, and the third part form a shape of a capital “H” with respect to a cross-sectional view of the semiconductor device structure; 
   a gate dielectric layer in contact with the first surface of the first portion and the second surface of the second portion; and   a gate electrode layer disposed on the gate dielectric layer.   
     
     
         13 . The semiconductor device structure of  claim 12 , wherein the dopant suppression layer comprises carbon or fluorine. 
     
     
         14 . The semiconductor device structure of  claim 13 , wherein the dopant suppression layer further comprises silicon, arsenic, or a combination thereof. 
     
     
         15 . The semiconductor device structure of  claim 14 , wherein the dopant suppression layer is silicon carbide, carbon doped silicon, or arsenic doped silicon carbide. 
     
     
         16 . The semiconductor device structure of  claim 13 , further comprising:
 a first source/drain feature in contact with the second part of the dopant suppression layer; and   a second source/drain feature in contact with the third part of the dopant suppression layer.   
     
     
         17 . The semiconductor device structure of  claim 13 , further comprising:
 a second channel layer formed of the first material, wherein the second channel layer is aligned with the first channel layer and in contact with the gate dielectric layer.   
     
     
         18 . A semiconductor device structure, comprising:
 a first channel layer formed of a first semiconductor material;   a second channel layer disposed adjacent and in parallel to the first channel layer, the second channel layer being formed of the first semiconductor material;   a first dopant suppression layer in contact with sidewalls and a bottom surface of the first channel layer;   a second dopant suppression layer in contact with sidewalls and top and bottom surfaces of the second channel layer, wherein the first and second dopant suppression layers each comprises carbon or fluorine;   a gate dielectric layer in contact with the first and second dopant suppression layers; and   a gate electrode layer disposed on the gate dielectric layer to surround portions of the first and second channel layers.   
     
     
         19 . The semiconductor device structure of  claim 18 , wherein each of the first dopant suppression layer and the second dopant suppression layer further comprises silicon, arsenic, or a combination thereof. 
     
     
         20 . The semiconductor device structure of  claim 18 , wherein the second dopant suppression layer contacting the sidewalls of the first channel comprises a first material, and the first dopant suppression layer contacting the top and bottom surfaces comprises a second material that is chemically different from the first material.