US2023100860A1PendingUtilityA1

Memory devices with reduced read disturbance effects

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Assignee: INTEL CORPPriority: Sep 24, 2021Filed: Sep 24, 2021Published: Mar 30, 2023
Est. expirySep 24, 2041(~15.1 yrs left)· nominal 20-yr term from priority
Inventors:Sou-Chi ChangNazila HaratipourShriram ShivaramanUygar E. AvciSarah AtanasovChristopher M. Neumann
H10W 90/00H10D 1/68H10B 53/30H10B 12/30H10B 53/40H10B 12/50H01L 25/0657H01L 27/11509H01L 27/11507H01L 27/10805
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Claims

Abstract

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A memory device, comprising:
 a capacitor stack that includes:
 a first electrode; 
 a second electrode; and 
 an Hf-based anti-ferroelectric (AFE) layer between the first electrode and the second electrode. 
   
     
     
         2 . The memory device of  claim 1 , wherein the Hf-based AFE layer comprises: Hf1-xZrxO2, where 0.5<x<1. 
     
     
         3 . The memory device of  claim 1 , wherein the Hf-based AFE layer comprises: La-doped Hf1-xZrxO2, or Ce-doped Hf1-xZrxO2, where 0.5<x<1, and wherein the Hf-based AFE layer has a doping concentration between 1% and 7%. 
     
     
         4 . The memory device of  claim 1 , further comprising an inter-level dielectric (ILD) layer coupled to the second electrode, wherein the ILD layer comprises TaN, RuO2, IrO2, ZrO2, or HfO2, and wherein the ILD layer has a thickness between 1 nm and 5 nm. 
     
     
         5 . The memory device of  claim 1 , further comprising a via coupled to the first electrode, second electrode, and Hf-based AFE layer. 
     
     
         6 . The memory device of  claim 1 , further comprising a TaN layer between the second electrode and the Hf-based AFE layer. 
     
     
         7 . The memory device of  claim 1 , wherein the first electrode or the second electrode comprise Mo. TiN, or W. 
     
     
         8 . The memory device of  claim 1 , wherein the Hf-based AFE layer has a thickness between 3 nm and 10 nm. 
     
     
         9 . The memory device of  claim 1 , wherein the first electrode or the second electrode has a thickness between 5 nm and 20 nm. 
     
     
         10 . The memory device of  claim 1 , further comprising a transistor coupled to the capacitor stack. 
     
     
         11 . A memory device, comprising:
 a capacitor stack that includes:
 a first electrode; 
 a second electrode; and 
 an Hf-based ferroelectric (FE) layer between the first electrode and the second electrode. 
   
     
     
         12 . The memory device of  claim 11 , wherein the Hf-based FE layer comprises: Hf1-xZrxO2, wherein x=0.4 to 0.6. 
     
     
         13 . The memory device of  claim 11 , wherein the Hf-based FE layer comprises: La-doped Hf1-xZrxO2, or Ce-doped Hf1-xZrxO2, wherein x=0.4 to 0.6. 
     
     
         14 . The memory device of  claim 13 , wherein the Hf-based FE layer has a doping concentration between 1% and 7%. 
     
     
         15 . The memory device of  claim 11 , wherein the Hf-based FE layer has a thickness between 3 nm and 10 nm. 
     
     
         16 . The memory device of  claim 11 , wherein the first electrode or the second electrode has a thickness between 5 nm and 20 nm. 
     
     
         17 . The memory device of  claim 11 , further comprising a via coupled to the first electrode, second electrode, and Hf-based FE layer. 
     
     
         18 . The memory device of  claim 11 , further comprising a TaN layer between the second electrode and the Hf-based FE layer. 
     
     
         19 . The memory device of  claim 11 , wherein the first electrode or the second electrode comprise: Mo, TiN, or W. 
     
     
         20 . The memory device of  claim 11 , further comprising a transistor coupled to the capacitor stack. 
     
     
         21 . The memory device of  claim 11 , further comprising an inter-level dielectric (ILD) layer coupled to the second electrode, wherein the ILD layer comprises TaN, RuO2, IrO2, ZrO2, or HfO2, and wherein the ILD layer has a thickness between 1 nm and 5 nm. 
     
     
         22 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including a memory device, comprising:
 a capacitor stack that includes:
 a first electrode; 
 a second electrode; and 
 an Hf-based anti-ferroelectric (AFE) layer between the first electrode and the second electrode. 
 
   
     
     
         23 . The computing device of  claim 22 , further comprising: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board. 
     
     
         24 . A computing device, comprising:
 a board; and   a component coupled to the board, the component including a memory device, comprising:
 a capacitor stack that includes:
 a first electrode; 
 a second electrode; and 
 an Hf-based ferroelectric (FE) layer between the first electrode and the second electrode. 
 
   
     
     
         25 . The computing device of  claim 24 , further comprising: a processor coupled to the board, a communication chip coupled to the board, or a camera coupled to the board.

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