Cmos finfet device having strained sige fins and a strained si cladding layer on the nmos channel

Abstract

Techniques and methods related to strained NMOS and PMOS devices without relaxed substrates, systems incorporating such semiconductor devices, and methods therefor may include a semiconductor device that may have both n-type and p-type semiconductor bodies. Both types of semiconductor bodies may be formed from an initially strained semiconductor material such as silicon germanium. A silicon cladding layer may then be provided at least over or on the n-type semiconductor body. In one example, a lower portion of the semiconductor bodies is formed by a Si extension of the wafer or substrate. By one approach, an upper portion of the semiconductor bodies, formed of the strained SiGe, may be formed by blanket depositing the strained SiGe layer on the Si wafer, and then etching through the SiGe layer and into the Si wafer to form the semiconductor bodies or fins with the lower and upper portions.

1 . A method for fabricating NMOS and PMOS FinFETs on a silicon substrate, the method comprising:
 forming a strained layer of silicon germanium onto the silicon substrate;   depositing a mask layer onto the strained layer of silicon germanium;   patterning the mask layer;   selectively removing a patterned portion of the mask layer;   selectively etching the silicon germanium and a depth of the underlying silicon substrate where the mask layer has been selectively removed, thereby forming fins where the mask layer has not been selectively removed and trenches where the mask layer has been selectively removed, the fins having a top portion comprising silicon germanium and a bottom portion comprising silicon;   depositing an insulation layer within the trenches;   forming a removeable cover layer over a first subset of the fins that are designated to become PMOS FinFETs, while leaving a second subset of the fins that are designated to become NMOS FinFETs without the removeable cover layer;   selectively forming a silicon germanium cap layer over the first subset of the fins that are designated to become PMOS FinFETs;   
     
     
         2 . The method of  claim 1  wherein forming the strained layer of silicon germanium onto the silicon substrate comprises:
 epitaxially growing the strained layer of silicon germanium onto the silicon substrate. 
 
     
     
         3 . The method of  claim 1 , further comprising:
 selectively forming a silicon cap layer over the second subset of the fins that are designated to become NMOS FinFETs,   
     
     
         4 . The method of  claim 3 , wherein selectively forming a silicon cap layer over the second subset of the fins that are designated to become NMOS FinFETs comprises:
 epitaxially growing the silicon cap layer onto the second subset of the fins hat are designated to become NMOS FinFETs, the method further comprising:   removing the removeable cover layer formed over the first subset of the fins that are designated to become PMOS FinFETs.   
     
     
         5 . The method of  claim 3 , wherein selectively forming a silicon cap layer over the second subset of the fins that are designated to become NMOS FinFETs comprises:
 epitaxially growing the silicon cap layer onto the second subset of the fins that are designated to become NMOS FinFETs.   
     
     
         6 . The method of  claim 1 , wherein the silicon germanium cap layer comprises silicon germanium having a first germanium concentration higher than a second germanium concentration of the strained layer of silicon germanium formed onto the silicon substrate. 
     
     
         7 . The method of  claim 6 , wherein the silicon germanium cap layer has a germanium content of at least 90%. 
     
     
         8 . The method of  claim 6 , wherein selectively forming the silicon germanium cap layer over the first subset of the fins that are designated to become PMOS FinFETs comprises:
 epitaxially growing the silicon germanium cap layer over the first subset of the fins that are designated to become PMOS FinFETs.   
     
     
         9 . The method of  claim 1 , further comprising:
 providing doped source and drain regions for a first subset of the fins that are designated to become PMOS FinFETs.   
     
     
         10 . The method of  claim 9 , wherein the doped source and drain regions for the first subset of the fins that are designated to become PMOS FinFETs comprises silicon germanium having a first germanium concentration higher than a second germanium concentration of the strained layer of silicon germanium formed onto the silicon substrate. 
     
     
         11 . The method of  claim 9 , wherein the doped source and drain regions for the first subset of the fins that are designated to become PMOS FinFETs has a germanium concentration of greater than 90%. 
     
     
         12 . The method of  claim 9 , wherein providing doped source and drain regions for a first subset of the fins that are designated to become PMOS FinFETs comprises:
 etching source and drain portions of the first subset of the fins that are designated to become PMOS FinFETs; and   depositing the doped source and drain portions of the first subset of the fins that are designated to become PMOS FinFETs.   
     
     
         13 . The method of  claim 12 , wherein depositing doped source and drain portions of the first subset of the fins that are designated to become PMOS FinFETs comprising:
 epitaxially growing the doped source and drain portions of the first subset of the fins that are designated to become PMOS FinFETs   
     
     
         14 . The method of  claim 9 , further comprising:
 providing doped silicon source and drain regions for a second subset of the fins that are designated to become NMOS FinFETs.   
     
     
         15 . The method of  claim 14 , wherein the doped source and drain regions for the second subset of the fins that are designated to become NMOS FinFETs comprises silicon. 
     
     
         16 . The method of  claim 14 , wherein providing doped source and drain regions for a first subset of the fins that are designated to become PMOS FinFETs comprises:
 etching source and drain portions of the second subset of the second that are designated to become NMOS FinFETs; and   depositing the doped source and drain portions of the second subset of the fins that are designated to become NMOS FinFETs.   
     
     
         17 . The method of  claim 16 , wherein depositing doped source and drain portions of the second subset of the fins that are designated to become NMOS FinFETs comprising:
 epitaxially growing the doped source and drain portions of the second subset of the fins that are designated to become NMOS FinFETs   
     
     
         18 . The method of  claim 1 , further comprising:
 forming a gate dielectric onto body portions of the fins; and   depositing a gate electrode onto gate dielectric.   
     
     
         19 . The method of  claim 18 , wherein forming gate dielectric onto body portions of the fins comprises:
 depositing a high-k dielectric onto the body portions of the fins.   
     
     
         20 . The method of  claim 1 , wherein the substrate is a silicon substrate with a top surface crystal orientation of  110 .