Self-Selecting Memory Cells Configured to Store More Than One Bit per Memory Cell

Abstract

Systems, methods and apparatus to program a memory cell to have a threshold voltage to a level representative of one value among more than two predetermined values. A first voltage pulse is driven across the memory cell to cause a predetermined current to go through the memory cell. The first voltage pulse is sufficient to program the memory cell to a level representative of a first value. To program the memory cell to a level representative of a second value, a second voltage pulse, different from the first voltage pulse, is driven across the memory cell within a time period of residual poling in the memory cell caused by the first voltage pulse.

What is claimed is: 
     
         1 . A device, comprising:
 a memory cell;   at least one voltage driver operable to apply voltage pulses in a first polarity and a second polarity; and   a circuit configured to control the at least one voltage drivers to drive voltage pulses according to more than two polarity patterns to respectively store more than two values in the memory cell.   
     
     
         2 . The device of  claim 1 , wherein to store a first value among the more than two values, a first pattern among the more than two polarity patterns is configured to drive a voltage pulse across the memory cell to cause at least a predetermined current to go through the memory cell in a first direction. 
     
     
         3 . The device of  claim 2 , wherein to store a second value among the more than two values, a second pattern among the more than two polarity patterns is configured to drive a voltage pulse across the memory cell to cause at least the predetermined current to go through the memory in a second direction different from the first direction. 
     
     
         4 . The device of  claim 3 , wherein to store a third value among the more than two values, a third pattern among the more than two polarity patterns is configured to:
 drive a first voltage pulse across the memory cell to cause at least the predetermined current to go through the memory cell in a first direction; and   drive a second voltage pulse, different from the first voltage pulse, across the memory cell.   
     
     
         5 . The device of  claim 4 , wherein the first voltage pulse is in the first polarity and the second voltage pulse is in the second polarity. 
     
     
         6 . The device of  claim 5 , wherein a duration of the second voltage pulse is no more than one tenth of a duration of the first voltage pulse. 
     
     
         7 . The device of  claim 4 , wherein the memory cell is connected between a first line and a second line;
 wherein the first voltage pulse includes a positive voltage of a magnitude applied to the first and a negative voltage of the magnitude applied to the second line; and   wherein the second voltage pulse includes the positive voltage of the magnitude applied to the first line and the negative voltage of a reduced magnitude applied to the second line.   
     
     
         8 . The device of  claim 7 , wherein the reduced magnitude is substantially reduced to zero. 
     
     
         9 . The device of  claim 4 , wherein the first voltage pulse is in the first polarity and of a first magnitude; and
 wherein the second voltage pulse is in the first polarity and of a half of the first magnitude.   
     
     
         10 . The device of  claim 4 , wherein the second voltage pulse is insufficient to place the memory cell in a conductive state. 
     
     
         11 . A method, comprising:
 applying, using at least one voltage driver, voltage pulses to a memory cell in a first polarity and a second polarity; and   controlling the at least one voltage drivers to drive voltage pulses according to more than two polarity patterns to respectively store more than two values in the memory cell.   
     
     
         12 . The method of  claim 11 , further comprising:
 storing into the memory cell a first value among the more than two values via applying a first pattern among the more than two polarity patterns, the first pattern including driving a voltage pulse across the memory cell to cause at least a predetermined current to go through the memory cell in a first direction.   
     
     
         13 . The method of  claim 12 , further comprising:
 storing into the memory cell a second value among the more than two values via applying a second pattern among the more than two polarity patterns, the second pattern including driving a voltage pulse across the memory cell to cause at least the predetermined current to go through the memory in a second direction different from the first direction.   
     
     
         14 . The method of  claim 13 , further comprising:
 storing into the memory cell a third value among the more than two values via applying a third pattern among the more than two polarity patterns, the third pattern including:
 driving a first voltage pulse across the memory cell to cause at least the predetermined current to go through the memory cell in a first direction; and 
 driving a second voltage pulse, different from the first voltage pulse, across the memory cell. 
   
     
     
         15 . The method of  claim 14 , wherein the first voltage pulse is in the first polarity and the second voltage pulse is in the second polarity. 
     
     
         16 . The method of  claim 15 , wherein a duration of the second voltage pulse is no more than one tenth of a duration of the first voltage pulse. 
     
     
         17 . The method of  claim 14 , wherein the memory cell is connected between a first line and a second line;
 wherein the first voltage pulse includes a positive voltage of a magnitude applied to the first and a negative voltage of the magnitude applied to the second line; and   wherein the second voltage pulse includes maintaining the positive voltage of the magnitude applied to the first line while reducing the negative voltage applied to the second line to zero.   
     
     
         18 . The method of  claim 14 , wherein the first voltage pulse is in the first polarity and of a first magnitude; and
 wherein the second voltage pulse is in the first polarity and of a half of the first magnitude.   
     
     
         19 . A device, comprising:
 a bitline;   a wordline;   a memory cell coupled to the bitline and the wordline;   a first voltage driver coupled to the wordline;   a second voltage driver coupled to the bitline; and   a circuit configured to control the first voltage driver and the second voltage driver to drive voltage pulses according to more than two polarity patterns to respectively store more than two values in the memory cell.   
     
     
         20 . The device of  claim 19 , wherein the more than two polarity patterns includes a pattern of:
 driving, by the first voltage driver, a positive voltage of a predetermined magnitude to the wordline for a first period of time; and   driving, by the second voltage driver, a negative voltage of the predetermined magnitude to the bitline for a second period of time that is shorter than the first period of time;   wherein the predetermined magnitude and the second period of time are configured to be sufficient to cause a predetermined amount of current to go through the memory cell.