Semiconductor structure having air gaps and method for manufacturing the same

Abstract

A method for manufacturing a semiconductor structure includes forming a trench in a dielectric structure; forming a spacer layer on a lateral surface of the dielectric structure exposed by the trench; after forming the spacer layer, forming a first electrically conductive feature in the trench; removing at least portion of the dielectric structure to form a recess; forming an etch stop layer in the recess and over the first electrically conductive feature; and after forming the etch stop layer, depositing a dielectric layer in the recess and over the first electrically conductive feature.

What is claimed is: 
     
         1 . A semiconductor structure, comprising:
 a first interconnect structure including at least one conductive element; and   a second interconnect structure disposed on the first interconnect structure, and including
 a plurality of first conductive features spaced apart from each other, at least one of the first conductive features being electrically connected to the at least one conductive element, respectively, 
 a plurality of spacer layers laterally covering the first conductive features; 
 an etch stop layer conformally covering the spacer layers and disposed over the first conductive features, and 
 a dielectric layer disposed on the etch stop layer. 
   
     
     
         2 . The semiconductor structure according to  claim 1 , further comprising a conductive capping layer disposed on the first conductive features and below the etch stop layer. 
     
     
         3 . The semiconductor structure according to  claim 1 , wherein the dielectric layer includes air gaps among the first conductive features. 
     
     
         4 . The semiconductor structure according to  claim 1 , wherein the etch stop layer includes a top portion disposed over the first conductive features, and a surrounding portion extending downwardly from the top portion to cover the spacer layers. 
     
     
         5 . The semiconductor structure according to  claim 4 , further comprising at least one second conductive feature which penetrates through the dielectric layer and the top portion of the etch stop layer so as to electrically connect to the at least one of the first conductive features, respectively, and which is positioned within the top portion of the etch stop layer. 
     
     
         6 . The semiconductor structure according to  claim 1 , wherein the spacer layers are separated from the dielectric layer by the etch stop layer. 
     
     
         7 . The semiconductor structure according to  claim 1 , wherein
 the dielectric layer includes a lower dielectric sub-layer disposed on the first interconnect structure, and an upper dielectric sub-layer disposed on the lower dielectric sub-layer; and   the at least one of the first conductive features includes a lower conductive sub-feature disposed in the lower dielectric sub-layer and electrically connected to the at least one conductive element, and an upper conductive sub-feature disposed in the upper dielectric sub-layer and connected to the lower conductive sub-feature.   
     
     
         8 . The semiconductor structure according to  claim 7 , wherein
 at least one of the spacer layers includes a lower spacer sub-layer laterally covering the lower conductive sub-feature, and an upper spacer sub-layer laterally covering the upper conductive sub-feature and separated from the lower spacer sub-layer; and   the etch stop layer covers the upper spacer sub-layer.   
     
     
         9 . The semiconductor structure according to  claim 2 , wherein the etch stop layer includes a top portion covering the conductive capping layer, and a surrounding portion extending downwardly from the top portion to cover the spacer layers. 
     
     
         10 . A semiconductor structure, comprising:
 a first interconnect structure including a conductive element;   a first conductive feature electrically connected to the conductive element;   a spacer layer laterally covering the first conductive feature;   a conductive capping layer disposed on the first conductive feature;   an etch stop layer conformally covering the spacer layer and the conductive capping layer; and   a dielectric layer surrounding the first conductive feature, the spacer layer, and the etch stop layer, and including an air gap adjacent to the first conductive feature.   
     
     
         11 . The semiconductor structure according to  claim 10 , wherein
 the dielectric layer includes a lower dielectric sub-layer disposed on the first interconnect structure, and an upper dielectric sub-layer disposed on the lower dielectric sub-layer; and   the first conductive feature includes an lower conductive sub-feature disposed in the lower dielectric sub-layer and electrically connected to the conductive element, and an upper conductive sub-feature disposed in the upper dielectric sub-layer and connected to the lower conductive sub-feature.   
     
     
         12 . The semiconductor structure according to  claim 11 , wherein
 the spacer layer includes a lower spacer sub-layer laterally covering the lower conductive sub-feature, and an upper spacer sub-layer laterally covering the upper conductive sub-feature and separated from the lower spacer sub-layer; and   the etch stop layer covers the upper spacer sub-layer.   
     
     
         13 . The semiconductor structure according to  claim 10 , wherein the etch stop layer includes a top portion disposed over the first conductive feature, and a surrounding portion extending downwardly from the top portion to cover the spacer layer. 
     
     
         14 . The semiconductor structure according to  claim 13 , wherein the conductive capping layer is disposed between the top portion of the etch stop layer and the first conductive feature. 
     
     
         15 . The semiconductor structure according to  claim 14 , further comprising a second conductive feature which penetrates through the dielectric layer, the top portion of the etch stop layer, and the conductive capping layer so as to electrically connect to the first conductive feature, and which is positioned within the top portion of the etch stop layer. 
     
     
         16 . The semiconductor structure according to  claim 13 , wherein the spacer layer is separated from the dielectric layer by the surrounding portion of the etch stop layer. 
     
     
         17 . The semiconductor structure according to  claim 10 , wherein the conductive capping layer includes a conductive carbon-based material, a conductive polymer, a conductive organic composite, a conductive ceramic composite, a conductive metal composite, or combinations thereof. 
     
     
         18 . A semiconductor structure, comprising:
 a semiconductor substrate; and   an interconnect structure disposed on the semiconductor substrate, and including
 a plurality of first conductive features spaced apart from each other, 
 a plurality of spacer layers laterally covering the first conductive features, 
 a conductive capping layer disposed on the first conductive features, 
 an etch stop layer conformally covering the spacer layers and the conductive capping layer, and 
 a dielectric layer disposed on the etch stop layer. 
   
     
     
         19 . The semiconductor structure according to  claim 18 , wherein the etch stop layer includes a top portion disposed on the conductive capping layer, and a surrounding portion extending downwardly from the top portion to cover the spacer layers. 
     
     
         20 . The semiconductor structure according to  claim 19 , further comprising at least one second conductive feature which penetrates through the dielectric layer, the top portion of the etch stop layer, and the conductive capping layer so as to electrically connect to the at least one of the first conductive features, respectively, and which is positioned within the top portion of the etch stop layer.