Semiconductor structure and method of manufacturing the same

Abstract

The present disclosure provides a semiconductor structure, including an N th metal layer, a bottom electrode over the N th metal layer, a magnetic tunneling junction (MTJ) over the bottom electrode, a top electrode over the MTJ, and an (N+M) th metal layer over the N th metal layer. N and M are positive integers. The (N+M) th metal layer surrounds a portion of a sidewall of the top electrode. A manufacturing method of forming the semiconductor structure is also provided.

1 .- 20 . (canceled) 
     
     
         21 . A method of fabricating a semiconductor structure, comprising:
 providing a substrate having a first metal layer with a first metal line in a memory region and a second metal line coplanar with the first metal line and disposed in a logic region;   providing a memory element having a bottom electrode, a magnetic tunneling junction (MTJ) layer and a top electrode over the first metal line;   depositing a first dielectric material surrounding the memory element;   depositing a second dielectric material over the first dielectric material in the memory region and extending to the logic region;   forming a first trench in the second dielectric material and the first dielectric material exposing a surface of the top electrode and forming a second trench in the second dielectric material of the logic region;   filling the first trench and the second trench with conductive material; and   planarizing the conductive material.   
     
     
         22 . The method of  claim 21 , wherein the depositing the first dielectric material includes depositing the first dielectric material extending to the logic region. 
     
     
         23 . The method of  claim 21 , wherein the depositing the first dielectric material extending to the logic region includes depositing the first dielectric material directly on a top surface of the second metal line. 
     
     
         24 . The method of  claim 21 , wherein after the depositing the second dielectric material and prior to forming the first trench and the second trench, an uppermost surface of the second dielectric material is lower in the logic region than in an uppermost surface of the second dielectric material in the memory region. 
     
     
         25 . The method of  claim 24 , wherein after the planarizing, an uppermost surface of the second dielectric material in the logic region is substantially coplanar with an uppermost surface of the second dielectric material in the memory region. 
     
     
         26 . The method of  claim 21 , wherein the planarizing the conductive material removes a portion of the second dielectric material. 
     
     
         27 . The method of  claim 21 , wherein the depositing the first dielectric material includes depositing the first dielectric material on the surface of the top electrode and a top surface of the second metal line. 
     
     
         28 . A semiconductor structure, comprising:
 a logic region, comprising:
 a first portion of an Nth metal layer; 
 a via extending upward from the first portion of the Nth metal layer; 
 a first portion of an (N+1)th metal layer extending from the via; 
 a first dielectric layer interfaces a bottom portion of the via; and 
 a second dielectric layer interfacing a top portion of the via and the (N+1)th metal layer; 
   a memory region, comprising:
 a second portion of the Nth metal layer; 
 a bottom electrode over the Nth metal layer; 
 a magnetic tunneling junction (MTJ) over the bottom electrode; 
 a top electrode over the MTJ; and 
 a second portion of the (N+1)th metal layer over the top electrode, N being a nonzero, positive integer; 
 a third dielectric layer interfacing sidewalls of a bottom portion of the top electrode; 
 the first dielectric layer interfacing sidewalls a middle portion of the top electrode; and 
   the second dielectric layer over the first dielectric layer and interfacing the second portion of the (N+1)th metal layer.   
     
     
         29 . The structure of  claim 28 , wherein the first dielectric layer interfaces a top surface of the first portion of the Nth metal layer. 
     
     
         30 . The structure of  claim 29 , wherein the second dielectric layer is disposed directly on the first dielectric layer in the logic region. 
     
     
         31 . The structure of  claim 30 , wherein the via extends through the second dielectric layer and the first dielectric layer. 
     
     
         32 . The structure of  claim 28 , wherein the MTJ has a circular shape in a top view. 
     
     
         33 . The structure of  claim 32 , wherein the third dielectric layer has a circular shape in the top view. 
     
     
         34 . A semiconductor structure, comprising:
 a memory region, comprising:
 a first portion of a Nth metal layer; 
 a bottom electrode over the Nth metal layer; 
 a magnetic tunneling junction (MTJ) over the bottom electrode; 
 a top electrode over the MTJ; and 
 a first portion of a (N+1)th metal layer over the top electrode, N being a nonzero, positive integer; 
 a first dielectric layer interfacing sidewalls of a bottom portion of the top electrode; 
 a second dielectric layer interfacing sidewalls a middle portion of the top electrode; and 
 a third dielectric layer over the first dielectric layer and under at least a portion of the second dielectric layer; 
   wherein the first dielectric layer and the third dielectric layer have a circular configuration in a top view.   
     
     
         35 . The semiconductor structure of  claim 34 , wherein the circular configuration of the first dielectric layer and the circular configuration of the third dielectric layer are concentric. 
     
     
         36 . The semiconductor structure of  claim 34 , wherein the MTJ has a circular configuration in the top view. 
     
     
         37 . The semiconductor structure of  claim 36 , wherein the circular configuration of the MTJ is concentric the circular configuration of first dielectric layer and the circular configuration of the third dielectric layer. 
     
     
         38 . The semiconductor structure of  claim 36 , wherein a diameter of the MTJ is about 1000 Angstroms. 
     
     
         39 . The semiconductor structure of  claim 34 , further comprising:
 a logic region, comprising:
 a second portion of the Nth metal layer; 
 a via extending upward from the second portion of the Nth metal layer; and 
 a second portion of the (N+1)th metal layer extending from the via, the second dielectric layer extends to the logic region, and wherein the via extends through the second dielectric layer. 
   
     
     
         40 . The semiconductor structure of  claim 39 , wherein the first portion of the Nth metal layer and the second portion of the Nth metal layer are coplanar.