Systems and methods for releveled bump planes for chiplets

Abstract

An integrated circuit and a method for designing an IC wherein the base or host chip is bonded to smaller chiplets via DBI technology. The bonding of chip to chiplet creates an uneven or multi-level surface of the overall chip requiring a releveling for future bonding. The uneven surface is built up with plating of bumps and subsequently releveled with various methods including planarization.

1 . (canceled) 
     
     
         2 . A chip assembly comprising:
 an integrated circuit (IC) chiplet directly electrically and physically coupled to an integrated circuit (IC) chip through a direct bonding region in an overlapping region between the IC chiplet and the IC chip; and   a plurality of posts comprising longer posts vertically extending from the IC chip and shorter posts shorter than the longer posts vertically extending from the IC chiplet.   
     
     
         3 . The chip assembly of  claim 2 , wherein the posts are embedded in a dielectric material forming a planarized surface at which the posts substantially coterminate. 
     
     
         4 . The chip assembly of  claim 3 , wherein the posts comprise plated posts selectively plated on seed layers. 
     
     
         5 . The chip assembly of  claim 4 , the plated posts have formed thereon on solder caps. 
     
     
         6 . The chip assembly of  claim 5 , wherein the planarized surface has formed thereover a redistribution layer for redirecting electrical signals from the posts. 
     
     
         7 . The chip assembly of  claim 2 , wherein a back side of the IC chiplet is directly electrically coupled to a front side of the IC chip without using an adhesive. 
     
     
         8 . The chip assembly of  claim 3 , wherein the front side of the IC chip and the backside of the IC chiplet are electrically connected by through silicon vias extending through the chiplet. 
     
     
         9 . The chip assembly of  claim 2 , wherein the IC chiplet is direct bonded to the IC chip along a bonded interface comprising bonded metallic regions and bonded non-metallic regions. 
     
     
         10 . A chip assembly comprising:
 an integrated circuit (IC) chiplet bonded to an integrated circuit (IC) chip without using an adhesive; and   a plurality of posts comprising longer posts vertically extending from the IC chip and shorter posts shorter than the longer posts vertically extending from the IC chiplet, wherein the posts terminate at a redistribution layer over the plurality of posts.   
     
     
         11 . The chip assembly of  claim 10 , wherein the posts are embedded in a dielectric material forming a planarized surface on which the redistribution layer is formed. 
     
     
         12 . The chip assembly of  claim 11 , wherein the posts comprise plated posts selectively plated on seed layers. 
     
     
         13 . The chip assembly of  claim 10 , wherein the IC chiplet is direct bonded to the IC chip along a bonded interface comprising bonded metallic regions and bonded non-metallic regions. 
     
     
         14 . The chip assembly of  claim 10 , wherein a back side of the IC chiplet is directly electrically coupled to a front side of the IC chip through a direct bonding region in an overlapping region between the IC chiplet and the IC chip. 
     
     
         15 . The chip assembly of  claim 14 , wherein the front side of the IC chip and the backside of the IC chiplet are electrically connected by through silicon vias extending through the chiplet. 
     
     
         16 . The chip assembly of  claim 10 , wherein the IC chiplet is direct bonded to the IC chip along a bonded interface comprising bonded metallic regions and bonded non-metallic regions. 
     
     
         17 . The chip assembly of  claim 10 , wherein the IC chiplet is selected from the group consisting of a serializer/deserializer chip, a memory chip and a parallel interface chip. 
     
     
         18 . An integrated chip assembly comprising:
 a first assembly comprising an integrated circuit (IC) chiplet directly coupled to an integrated circuit (IC) chip through a direct bonding region in an overlapping region between the IC chiplet and the IC chip; and   a second assembly electrically connected to the first assembly by a plurality of a plurality of posts comprising longer posts vertically extending from the IC chip and shorter posts shorter than the longer posts vertically extending from the IC chiplet.   
     
     
         19 . The integrated chip assembly of  claim 18 , wherein the second assembly comprises one or more of another IC chip, an interposer and a substrate. 
     
     
         20 . The integrated chip assembly of  claim 18 , wherein the posts are embedded in a dielectric material forming a planarized surface at which the posts substantially coterminate. 
     
     
         21 . The integrated chip assembly of  claim 20 , wherein the planarized surface has formed thereover a redistribution layer for redirecting electrical signals from the posts. 
     
     
         22 . The integrated chip assembly of  claim 18 , wherein the IC chiplet is direct bonded to the IC chip along a bonded interface comprising bonded metallic regions and bonded non-metallic regions.