Stacked multi-gate device with reduced contact resistance and methods for forming the same

Abstract

Method to form low-contact-resistance contacts to source/drain features is provided. A method of the present disclosure includes receiving a workpiece including an opening that exposes a surface of an n-type source/drain feature and a surface of a p-type source/drain feature, lateral epitaxial structures etching on the n-type source/drain feature creating the offset from the sidewall of the dielectric layer, depositing a silicide layer and the offset between etched epitaxial structures and sidewall of the dielectric layer is eliminated. The lateral epitaxial structures etching includes a reactive-ion etching (RIE) process and an atomic layer etching (ALE) process.

What is claimed is: 
     
         1 . A method, comprising:
 forming a bottom-tier transistor comprising a first channel layer, a first gate structure around the first channel layer, and a plurality of first source/drain regions on opposite sides of the first channel layer;   forming a dielectric layer over the first source/drain regions of the bottom-tier transistor;   forming a top-tier transistor over the bottom-tier transistor, the top-tier transistor comprising a second channel layer, a second gate structure around the second channel layer, and a plurality of second source/drain regions on opposite sides of the second channel layer and over the dielectric layer;   etching a one of the second source/drain regions of the top-tier transistor and the dielectric layer to form an opening exposing one of the first source/drain regions of the bottom-tier transistor;   after forming the opening, laterally trimming the one of the second source/drain regions of the top-tier transistor through the opening;   forming a metal silicide on the trimmed one of the second source/drain regions; and   forming a source/drain contact in the opening.   
     
     
         2 . The method of  claim 1 , wherein laterally trimming the one of the second source/drain regions is performed by using a fluorine-based enchant or a chlorine-based enchant. 
     
     
         3 . The method of  claim 1 , wherein after the laterally trimming, the one of the second source/drain regions has a sidewall offset from a sidewall of the dielectric layer in the opening by a non-zero distance. 
     
     
         4 . The method of  claim 1 , wherein the metal silicide is in contact with a top surface of the dielectric layer exposed from the trimmed one of the second source/drain regions. 
     
     
         5 . The method of  claim 1 , wherein laterally trimming the one of the second source/drain regions is performed by an isotropic dry etching process. 
     
     
         6 . The method of  claim 1 , wherein laterally trimming the one of the second source/drain regions is performed by a dry etching process with a bottom bias power lower than a bottom bias power used in etching the one of the second source/drain regions. 
     
     
         7 . The method of  claim 1 , wherein laterally trimming the one of the second source/drain regions is performed by a dry etching process with a bottom bias power less than about 50 W/cm 2 . 
     
     
         8 . The method of  claim 1 , wherein laterally trimming the one of the second source/drain regions is performed by introducing an oxygen precursor at a flow rate lower than a flow rate of an oxygen precursor used in etching the one of the second source/drain regions. 
     
     
         9 . The method of  claim 1 , wherein laterally trimming the one of the second source/drain regions is performed by introducing an oxygen-free precursor on the one of the second source/drain regions. 
     
     
         10 . The method of  claim 1 , wherein etching the one of the second source/drain regions and laterally trimming the one of the second source/drain regions are in-situ performed. 
     
     
         11 . A method, comprising:
 forming a first semiconductive nanostructure, and a second semiconductive nanostructure vertically arranged with respect to the first semiconductive nanostructure;   forming a plurality of first epitaxial structures on opposite sides of the first semiconductive nanostructure, and a plurality of second epitaxial structures on opposite sides of the second semiconductive nanostructure;   forming a dielectric layer over the second epitaxial structures;   forming a first gate wrapping around the first semiconductive nanostructure, and a second gate wrapping around the second semiconductive nanostructure;   etching through the dielectric layer and one of the second epitaxial structures to form an opening exposing the one of the first epitaxial structures;   etching a sidewall of the one of the second epitaxial structures to create an offset from a sidewall of the dielectric layer within the opening;   after creating the offset from the sidewall of the dielectric layer within the opening, forming a silicide on the sidewall of the one of the second epitaxial structures; and   filling a contact material in the opening.   
     
     
         12 . The method of  claim 11 , wherein the silicide is in contact with a bottom surface of the dielectric layer exposed from the one of the second epitaxial structures. 
     
     
         13 . The method of  claim 11 , wherein the contact material is in contact with a bottom surface of the dielectric layer exposed from the one of the second epitaxial structures. 
     
     
         14 . The method of  claim 11 , wherein creating the offset from the sidewall of the dielectric layer within the opening is performed ex-situ with etching through the dielectric layer and the one of the second epitaxial structures. 
     
     
         15 . The method of  claim 11 , wherein creating the offset from the sidewall of the dielectric layer within the opening is performed by a dry etching process without a bias power. 
     
     
         16 . A semiconductor structure, comprising:
 a first transistor comprising:
 first semiconductor sheets; 
 a first gate structure surrounding each of the first semiconductor sheets; and 
 first source/drain structures on either side of each of the first semiconductor sheets; 
   a second transistor over the first transistor, the second transistor comprising:
 second semiconductor sheets; 
 a second gate structure surrounding each of the second semiconductor sheets; and 
 second source/drain structures on either side of each of the second semiconductor sheets; and 
   a source/drain contact extending through one of the second source/drain structures of the second transistor to one of the first source/drain structures of the first transistor, the source/drain contact comprising:   a first profile having a first sidewall and a second sidewall opposing the first sidewall; and   a second profile over the first profile and having a third sidewall and a fourth sidewall opposing the third sidewall, wherein at a boundary of the first profile and the second profile, a width between the third sidewall and the fourth sidewall is greater than a width between the first sidewall and the second sidewall by a non-zero offset value.   
     
     
         17 . The semiconductor structure of  claim 16 , further comprising a silicide layer interfacing the second profile of the source/drain contact. 
     
     
         18 . The semiconductor structure of  claim 17 , wherein the silicide layer is spaced apart from the first profile of the source/drain contact. 
     
     
         19 . The semiconductor structure of  claim 16 , wherein the source/drain contact further comprises a third profile over the second profile and having a fifth side wall and a sixth sidewall opposing the fifth sidewall, and wherein at a boundary of the third profile and the second profile, a width between the fifth sidewall and the sixth sidewall is less than the width between the third sidewall and the fourth sidewall. 
     
     
         20 . The semiconductor structure of  claim 16 , wherein along a vertical direction, a variation in the width between the first sidewall and the second sidewall of the first profile is different from a variation in the width between the third sidewall and the fourth sidewall of the second profile.