Method for manufacturing capacitor of semiconductor memory device by two-step thermal treatment

Abstract

A method for manufacturing a capacitor of a semiconductor memory device by a two-step thermal treatment is provided. A lower electrode is formed on a semiconductor substrate. A dielectric layer is formed over the lower electrode. An upper electrode formed of a noble metal is formed over the dielectric layer. The resultant having the upper electrode undergoes a first thermal treatment under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., which is lower than the oxidation temperature of the upper electrode. The first thermally treated resultant undergoes a second thermal treatment under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., which is higher than the first temperature.

That which is claimed is:  
     
       1. A method for manufacturing a capacitor of a semiconductor memory device comprising: 
       forming a lower electrode on a semiconductor substrate;  
       forming a dielectric layer over the lower electrode;  
       forming an upper electrode of a noble metal over the dielectric layer;  
       performing a first thermal treatment on the resultant having the upper electrode under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 200-600° C., and lower than the oxidation temperature of the upper electrode; and  
       performing a second thermal treatment on the first thermally treated resultant under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 300-900° C., and higher than the first temperature.  
     
     
       2. The method of  claim 1 , wherein the lower electrode is formed of a doped polysilicon, a metal, a conductive metal nitride, or a conductive metal oxide. 
     
     
       3. The method of  claim 2 , wherein the lower electrode is formed of a single layer of a doped polysilicon, TiN, TaN, WN, W, Pt, Ru, Ir, RuO 2 , or IrO 2 , or a complex layer thereof. 
     
     
       4. The method of  claim 1 , wherein the dielectric layer is formed of a single layer of Ta 2 O 5 , TiO 2 , (Ba, Sr)TiO 3  (BST), StTiO 3  (ST), SiO 2 , Si 3 N 4 , or PbZrTiO 3  (PZT), or a complex layer thereof. 
     
     
       5. The method of  claim 1 , wherein the upper electrode is formed of Ru, Pt, Ir, RuO 2 , or IrO 2 . 
     
     
       6. The method of  claim 1 , wherein the first atmosphere of the first thermal treatment step includes oxygen having a concentration of 0.01-100 volume %. 
     
     
       7. The method of  claim 1 , wherein the first atmosphere of the first thermal treatment step includes O 2 , N 2 O, or O 3  gas. 
     
     
       8. The method of  claim 1 , wherein the first atmosphere of the first thermal treatment step further includes inert gas. 
     
     
       9. The method of  claim 1 , wherein the second atmosphere of the second thermal treatment step is an inert gas atmosphere. 
     
     
       10. The method of  claim 1 , wherein the second atmosphere of the second thermal treatment step is a high vacuum atmosphere. 
     
     
       11. The method of  claim 1 , wherein the first thermal treatment step is performed in a rapid thermal processing (RTP) furnace. 
     
     
       12. The method of  claim 1 , wherein the first and second thermal treatment steps are performed in-situ in the same chamber. 
     
     
       13. The method of  claim 1 , after forming the lower electrode, further comprising: 
       forming a silicon nitride layer covering the lower electrode.  
     
     
       14. The method of  claim 13 , wherein the step of forming the silicon nitride layer includes thermally treating the lower electrode under an NH 3  atmosphere. 
     
     
       15. The method of  claim 13 , wherein the silicon nitride layer is formed by a chemical vapor deposition (CVD) method. 
     
     
       16. The method of  claim 13 , wherein the silicon nitride layer is formed to have a thickness of 5-30 Å. 
     
     
       17. The method of  claim 1 , after the step of forming a dielectric layer, further comprising: 
       thermally treating the dielectric layer.  
     
     
       18. The method of  claim 17 , wherein the step of forming the dielectric layer is performed under an atmosphere including oxygen. 
     
     
       19. The method of  claim 18 , wherein the step of thermally treating the dielectric layer is performed at the temperature of 200-800° C. 
     
     
       20. The method of  claim 17 , wherein the step of thermally treating the dielectric layer is performed under an atmosphere without oxygen. 
     
     
       21. The method of  claim 20 , wherein the step of thermally treating the dielectric layer is performed at a temperature of 500-800° C. 
     
     
       22. A method for manufacturing a capacitor of a semiconductor memory device comprising: 
       forming a lower electrode on a semiconductor substrate;  
       forming a dielectric layer formed of a Ta 2 O 5  layer over the lower electrode;  
       thermally treating the dielectric layer;  
       forming an upper electrode of Ru over the thermally treated dielectric layer;  
       performing a first thermal treatment on the resultant having the upper electrode under a first atmosphere including oxygen at a first temperature which is selected to be within a range of 300-500° C., and lower than the oxidation temperature of the upper electrode; and  
       performing a second thermal treatment on the first thermally treated resultant under a second atmosphere without oxygen at a second temperature which is selected to be within a range of 500-700° C., and higher than the first temperature.  
     
     
       23. The method of  claim 22 , wherein the lower electrode is formed of a doped polysilicon, a metal, a conductive metal nitride, or a conductive metal oxide. 
     
     
       24. The method of  claim 23 , wherein the lower electrode is formed of a single layer of a doped polysilicon, TiN, TaN, WN, W, Pt, Ru, Ir, RuO 2 , or IrO 2 , or a complex layer thereof. 
     
     
       25. The method of  claim 22 , wherein the step of thermally treating the dielectric layer is performed under an atmosphere including oxygen. 
     
     
       26. The method of  claim 25 , wherein the step of thermally treating the dielectric layer is performed at a temperature of 200-800° C. 
     
     
       27. The method of  claim 22 , wherein the step of thermally treating the dielectric layer is performed under an atmosphere without oxygen. 
     
     
       28. The method of  claim 27 , wherein the step of thermally treating the dielectric layer is performed at the temperature of 500-800° C. 
     
     
       29. The method of  claim 22 , wherein the first atmosphere of the first thermal treatment includes oxygen having a concentration of 0.01-100 volume %. 
     
     
       30. The method of  claim 22 , wherein the first atmosphere of the first thermal treatment step includes O 2 , N 2 O, or O 3  gas. 
     
     
       31. The method of  claim 22 , wherein the first thermal treatment step is performed at a temperature of 350-450° C. 
     
     
       32. The method of  claim 22 , wherein the first atmosphere of the first thermal treatment further includes inert gas. 
     
     
       33. The method of  claim 22 , wherein the second atmosphere of the second thermal treatment step is an inert gas atmosphere. 
     
     
       34. The method of  claim 22 , wherein the second thermal treatment step is performed at a temperature of 600-650° C. 
     
     
       35. The method of  claim 22 , wherein the first and second thermal treatment steps are performed in-situ in the same chamber. 
     
     
       36. The method of  claim 22 , after forming the lower electrode, further comprising: 
       forming a silicon nitride layer covering the lower electrode.  
     
     
       37. A method of fabricating an integrated circuit capacitor, comprising the steps of: 
       forming a lower capacitor electrode on a semiconductor substrate;  
       forming a dielectric layer on the lower capacitor electrode;  
       forming an upper capacitor electrode comprising a noble metal on the dielectric layer, opposite the lower capacitor electrode;  
       exposing the upper capacitor electrode to an oxygen containing atmosphere having a first temperature in a range between 200° C. and a first temperature limit that is less than an oxidation temperature of the upper capacitor electrode; and then  
       exposing the upper capacitor electrode to an oxygen deficient atmosphere having a second temperature above the oxidation temperature of the upper capacitor electrode.  
     
     
       38. The method of  claim 37 , wherein said step of forming an upper capacitor electrode is preceded by the step of increasing the crystallinity of the dielectric layer by thermally treating the dielectric layer in an oxygen deficient atmosphere. 
     
     
       39. The method of  claim 37 , wherein the oxygen deficient atmosphere comprises an inert gas selected from the group consisting of argon and nitrogen. 
     
     
       40. The method of  claim 37 , wherein said step of forming a dielectric layer is preceded by the step of forming a silicon nitride layer on the lower capacitor electrode. 
     
     
       41. The method of  claim 37 , wherein said step of exposing the upper capacitor electrode to an oxygen containing atmosphere comprises exposing the upper capacitor electrode to an oxygen containing atmosphere for a duration sufficient to cause migration of oxygen through the upper capacitor electrode and into the dielectric layer. 
     
     
       42. A method of fabricating an integrated circuit capacitor, comprising the steps of: 
       forming a lower capacitor electrode on a semiconductor substrate;  
       forming a dielectric layer on the lower capacitor electrode;  
       forming an upper capacitor electrode, comprising a metal or a metal oxide, on the dielectric layer;  
       exposing the upper capacitor electrode to an oxygen containing atmosphere having a first temperature in a range between 200° C. and a first temperature limit that is less than an oxidation temperature of the upper capacitor electrode; and then  
       exposing the upper capacitor electrode to an oxygen deficient atmosphere having a second temperature above the oxidation temperature of the upper capacitor electrode.  
     
     
       43. The method of  claim 42 , wherein the metal or metal oxide is an electrically conductive material selected from the group consisting of Ru, Pt, Ir, RuO 2  and IrO 2 . 
     
     
       44. The method of  claim 42 , wherein the oxygen deficient atmosphere comprises an inert gas selected from the group consisting of argon and nitrogen. 
     
     
       45. The method of  claim 42 , wherein said step of forming a dielectric layer is preceded by the step of forming a silicon nitride layer on the lower capacitor electrode. 
     
     
       46. The method of  claim 42 , wherein said step of exposing the upper capacitor electrode to an oxygen containing atmosphere comprises exposing the upper capacitor electrode to an oxygen containing atmosphere for a duration sufficient to cause migration of oxygen through the upper capacitor electrode and into the dielectric layer. 
     
     
       47. A method of fabricating an integrated circuit capacitor, comprising the steps of: 
       forming a lower capacitor electrode on a semiconductor substrate;  
       forming a dielectric layer on the lower capacitor electrode;  
       forming an upper capacitor electrode, comprising a metal or a metal oxide, on the dielectric layer;  
       exposing the upper capacitor electrode to an oxygen containing atmosphere having a first temperature in a range between 200° C. and a first temperature limit that is less than an oxidation temperature of the upper capacitor electrode, for a sufficient duration to accumulate oxygen atoms at an interface between the upper capacitor electrode and the dielectric layer; and then  
       exposing the upper capacitor electrode to an oxygen deficient atmosphere having a second temperature that is higher than the oxidation temperature of the upper capacitor electrode and also sufficiently high to cure the dielectric layer through diffusion of the accumulated oxygen into oxygen vacancies within the dielectric layer.  
     
     
       48. The method of  claim 47 , wherein said step of forming a dielectric layer is preceded by the step of forming a silicon nitride layer on the lower capacitor electrode.