Cmos-compatible read only memory and method for fabricating the same

Abstract

A CMOS-compatible read only memory (ROM) includes a first single-poly PMOS transistor that is serially electrically connected to a second single-poly PMOS transistor for recording digital data “1” or digital data “0”. The first and second single-poly PMOS transistors are both formed on an N-well of a P-type substrate. The first single-poly PMOS transistor includes a select gate electrically connected to a word line, a first P+ source doping region electrically connected to a source line, and a first P+ drain doping region. The second single-poly PMOS transistor includes a floating gate, a second P+ source doping region electrically connected to the first P+ drain doping region, and a second P+ drain doping region electrically connected to a bit line. The second P+ source doping region and the second P+ drain doping region define a floating gate channel region under the floating gate. A fast FPLD-to-ROM conversion method is also disclosed. After the final software code is fixed and the addresses where the memory units to be coded are determined, the FPLD are transformed into a ROM by either changing the layout of a photo mask that is used to define polysilicon gates to cancel the pre-selected floating gates according to the fixed software code, or by ion implanting the pre-selected floating gate channel regions underneath those floating gates where the memory units are to be coded.

What is claimed is:  
     
       1. A read only memory (ROM) cell unit comprising: 
       a P type substrate;  
       an N well disposed in the P type substrate;  
       non-stacked gate electrode PMOS select transistor formed on the N well, the non-stacked gate electrode PMOS select transistor comprising select gate electrically connected to a word line, a first P+ source doping region electrically connected to a source line, and a first P+ drain doping region; and  
       a non-stacked gate electrode PMOS floating gate transistor formed on the N wall and serially electrically connected to the non-stacked gate electrode PMOS select transistor, the non-stacked gate electrode PMOS floating gate transistor comprising a floating gate, a second P+ source doping region electrically connected to the first P+ drain doping region, and a second P+ drain doping region electrically connected to a bit line, wherein the second P+ source doping region and the second P+ source doping region define a floating gate channel;  
       wherein P type impurities are implanted into the floating gate P channel, thereby turning the non-stacked gate electrode PMOS floating gate transistor into a depletion mode transistor for storing logic data “1”.  
     
     
       2. The ROM cell unit of  claim 1  wherein the floating gate P channel is doped to a concentration of between 10 16 -10 18  cm −3 . 
     
     
       3. The ROM cell unit of  claim 1  wherein the second P+ source doping region and the first P+ drain doping region are merged into a contiguous region. 
     
     
       4. The ROM cell unit of  claim 1  wherein the P type impurities are boron ions. 
     
     
       5. A read only memory (ROM) cell unit comprising: 
       a non-stacked gate electrode MOS select transistor comprising a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region; and  
       a non-staked gate electrode MOS floating gate transistor serially electrically connected to the non-stacked gate electrode MOS select transistor, the non-stacked gate electrode MOS floating gate transistor comprising a floating gate, a second source doping region electrically connected to the first drain doping region, and a second drain doping region electrically connected to a bit line, wherein the second source doping region and the second source doping region define a floating gate channel.  
     
     
       6. The ROM cell unit of  claim 5  is a mask ROM. 
     
     
       7. The ROM cell unit of  claim 5  wherein impurities are implanted into the floating gate channel, thereby turning the non-stacked gate electrode MOS floating gate transistor into a depletion mode transistor for storing digital data “1”. 
     
     
       8. The ROM cell unit of  claim 7  wherein the floating gate channel is doped to a concentration of between 10 16 -10 18  cm −3 . 
     
     
       9. The ROM cell unit of  claim 5  wherein the non-stacked gate electrode MOS select transistor and the non-stacked gate electrode MOS floating gate transistor are both single-poly PMOS transistors. 
     
     
       10. The ROM cell unit of  claim 5  wherein the second source doping region and the first drain doping region are merged into a contiguous region. 
     
     
       11. A read only memory (ROM) coded with binary code, the ROM comprising: 
       an array of field programmable logic devices (FPLDs) comprising a plurality of non-stacked date electrode MOS select transistors in one column, each of the non-stacked gate electrode MOS select transistor comprising a select gate electrically connected to a word line, a first source doping region electrically connected to a source line, and a first drain doping region;  
       a non-stacked gate electrode MOS floating gate transistor serially electrically connected to the corresponding non-stacked gate electrode MOS select transistor in the column at an address for storing logic data “0”, the non-stacked gate electrode MOS floating gate transistor comprising a floating gate, a second source doping region electrically connected to the first drain doping region, and a second drain doping region electrically connected to a bit line; and  
       a resistor electrically connected the first drain doping, region of the corresponding MOS select transistor in the column at an address for storing logic data “1” with the bit line.  
     
     
       12. The ROM of  claim 11  wherein the resistor is an ion doping region connecting the first drain doping region of the corresponding non-stacked gate electrode MOS select transistor in the column at an address for storing logic data “1” with the bit line, and wherein the ion doping region has the same polarity as the polarity of the first source doping region and the polarity of the first drain doping region. 
     
     
       13. A read only memory (ROM) coded with binary code, the ROM comprising: 
       an array of field programmable logic devices (FPLDs) comprising a plurality of non stacked gate electrode PMOS select transistors in one column, each of the non-stacked gate electrode PMOS select transistor comprising a select gate electrically connected to a word line, a first P+ source doping region electrically, connected to a source line, and a first P+ drain doping region;  
       a non-stacked gate electrode PMOS floating gate transistor serially electrically connected to the corresponding non-stacked gate electrode PMOS select transistor in the column at an address for storing logic data “0”, the non-stacked gate electrode PMOS floating gate transistor comprising a single-poly floating gate, a second P+ source, doping region electrically connected to the first P+ drain doping region, and second P+ drain doping region electrically connected to a bit line; and  
       a P doping region formed in a cancelled floating gate channel region at an address for storing logic data “1”, the P doping region acting as a resistor electrically connected the first P drain doping region of the corresponding non-stacked gate electrode PMOS select transistor of the column at the address for storing logic data “1” with the bit line, wherein there is no floating gate above the P doping region.  
     
     
       14. The read only memory (ROM) coded with binary code of  claim 13  wherein the second source P+ doping region and the first P+ drain doping region are merged into a contiguous region.