Method for fabricating a vertical NROM cell

Abstract

A method for fabricating a vertical nitride read-only memory (NROM) cell. A substrate having at least one trench is provided. A spacer is formed over the sidewall of the trench. Subsequently, ion implantation is performed on the substrate using the spacer as a mask to form doping areas as bit lines in the substrate near its surface and the bottom of the trench. Bit line oxides are formed over each of the doping areas. After the spacer is removed, a conformable insulating layer as gate dielectric is deposited on the sidewall of the trench and the surface of the bit line oxide. Finally, a conductive layer as a word line is deposited over the insulating layer and fills in the trench.

1. A vertical nitride read-only memory (NROM) cell, comprising:
 a substrate having at least one trench; 
 bit lines formed in the substrate near its surface adjacent to the trench and near the bottom of the trench; 
 bit line oxides disposed over each of the bit lines; 
 a gate dielectric layer conformably formed on and in direct contact with the substrate surface that constitutes sidewalls of the trench and the surface of the bit line oxide; and 
 a word line disposed over the gate dielectric and filled in the trench. 
 
   
   
     2. The cell as claimed in  claim 1 , wherein the trench has a depth of about 1400˜1600 Å. 
   
   
     3. The cell as claimed in  claim 1 , wherein the bit lines are formed by phosphorus ion implantation. 
   
   
     4. The cell as claimed in  claim 1 , wherein the bit line oxides are formed by thermal oxidation. 
   
   
     5. The cell as claimed in  claim 1 , wherein the bit line oxides have a thickness of about 500˜700 Å. 
   
   
     6. The cell as claimed in  claim 1 , wherein the gate dielectric layer is an oxide-nitride-oxide layer. 
   
   
     7. The cell as claimed in  claim 1 , wherein the word line is polysilicon.