Memory device and fabrication method thereof

Abstract

A memory device and fabricating method thereof. In the memory device of the present invention, a substrate has a plurality of deep trenches, wherein the deep trenches formed in the adjacent rows are staggered. A deep trench capacitor and a control gate are disposed in each deep trench successively. Word lines are disposed on the control gates respectively, and each word line is electrically coupled to the control gate thereunder. Diffusion regions are disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors. Each diffusion region is electrically connected to the surrounding deep trench capacitor. Active areas are disposed on the rows of the control gates respectively along a second direction. The regions where each active area overlaps the control gates have at least one indentation.

1. A memory device, comprising:
 a substrate with a plurality of deep trenches, wherein the deep trenches in adjacent rows are staggered; 
 a plurality of deep trench capacitors disposed in the deep trenches of the substrate respectively; 
 a plurality of control gates disposed on the deep trench capacitors respectively; 
 a plurality of word lines disposed on the control gates respectively along a first direction, each word line being electrically coupled to the control gate thereunder; 
 a plurality of diffusion regions disposed in the substrate and surrounding the deep trenches respectively to serve as sources of vertical transistors, wherein each diffusion region is electrically connected to the surrounding deep trench capacitor; 
 a plurality of active areas disposed on the rows of the control gates respectively along a second direction, wherein the diffusion regions where each active area overlaps the control gates have at least one indentation; and 
 a plurality of drains disposed in the active areas beside each word line. 
 
   
   
     2. The memory device as claimed in  claim 1 , wherein the first direction is essentially perpendicular to the second direction. 
   
   
     3. The memory device as claimed in  claim 1 , wherein each active area has normal portions and recessed portions, each recessed portion is disposed between two normal portions, and each of the recessed portions overlaps one of the control gates thereunder and has an indentation on both sides. 
   
   
     4. The memory device as claimed in  claim 3 , wherein each normal portion has a first width, and each recessed portion has a second width smaller than the first width. 
   
   
     5. The memory device as claimed in  claim 4 , wherein each normal portion has a lateral surface on both side, and each recessed portion has two slanted surfaces and a plane surface, and, relative to the lateral surface, each plane surface has a width diminution. 
   
   
     6. The memory device as claimed in  claim 5 , wherein the lateral surface relative to the slanted surface is has an angle of 135°. 
   
   
     7. The memory device as claimed in  claim 1 , wherein the word lines are composed of polysilicon. 
   
   
     8. The memory device as claimed in  claim 1 , further comprising a plurality of bit lines disposed on the active areas, and electrically coupled to the drains thereunder respectively.