Method of manufacturing a transistor

Abstract

A method of manufacturing a transistor according to some embodiments includes sequentially forming a dummy gate oxide layer and a dummy gate electrode on an active region of a semiconductor substrate, ion-implanting a first conductive impurity into source/drain regions to form first impurity regions, and ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions. The method includes forming a pad polysilicon layer on the source/drain regions, sequentially removing the pad polysilicon layer and the dummy gate electrode from a gate region of the semiconductor substrate, annealing the semiconductor substrate, and ion-implanting a second conductive impurity to form a third impurity region in the gate region. The method includes removing the dummy gate oxide layer, forming a gate insulation layer, and forming a gate electrode on the gate region.

1. A method of manufacturing a transistor, comprising:
 sequentially forming a dummy gate oxide layer, a dummy gate electrode, and a dummy gate upper insulation layer on a semiconductor substrate; 
 ion-implanting first impurities into source/drain regions provided on both sides of the dummy gate electrode to form first impurity regions; 
 forming spacers on sidewalls of the dummy gate electrode; 
 ion-implanting first impurities using the spacer as an ion implantation mask to form second impurity regions that are overlapped by the first impurity regions; 
 depositing pad polysilicon layers on the second impurity regions, the pad polysilicon layers in contact with the spacers; 
 removing the dummy gate upper insulation layer and an upper portion of the spacer; 
 removing the dummy gate electrode; 
 annealing the semiconductor substrate; 
 ion-implanting second impurities into a gate region of the semiconductor substrate to form a third impurity region, the second impurities having a conductivity type opposite that of the first impurities; 
 removing the dummy gate oxide layer; 
 forming a gate insulation layer; and 
 forming a gate electrode on the gate region. 
 
   
   
     2. The method of  claim 1 , further comprising depositing a device isolation film in a trench in the semiconductor substrate to define a cell region of the substrate and a core/perimeter region of the substrate. 
   
   
     3. The method of  claim 2 , wherein depositing the device isolation film comprises:
 sequentially forming a pad oxide layer, a molding polysilicon layer, and a hard mask layer on the semiconductor substrate; 
 depositing a photoresist on the hard mask layer; 
 patterning the photoresist to partially expose the hard mask layer; 
 partially etching the molding polysilicon layer, the pad oxide layer, and the semiconductor substrate by using the photoresist as an etching mask to form the trench; and 
 thermally oxidizing an interior of the trench to form the device isolation film. 
 
   
   
     4. The method of  claim 1 , wherein sequentially forming the dummy gate oxide layer, the dummy gate electrode, and the dummy gate upper insulation layer comprises:
 depositing a photoresist on the dummy gate upper insulation layer; 
 patterning the photoresist; 
 partially exposing the dummy gate electrode by etching the dummy gate upper insulation layer using the photoresist as an etch mask; 
 partially exposing the dummy gate oxide layer by etching the dummy gate electrode using the dummy gate upper insulation layer as an etch mask, thus forming the dummy gate electrode on a gate region; and 
 removing the photoresist. 
 
   
   
     5. The method of  claim 1 , wherein forming the dummy gate oxide layer comprises performing a wet type thermal oxidation process. 
   
   
     6. The method of  claim 1 , wherein forming the dummy gate oxide layer comprises forming the dummy gate oxide layer to a thickness of 30 Å to 80 Å. 
   
   
     7. The method of  claim 1 , wherein forming the dummy gate electrode comprises forming the dummy gate electrode of silicon germanium. 
   
   
     8. The method of  claim 1 , wherein forming the dummy gate upper insulation layer comprises forming the dummy gate upper insulation layer of silicon nitride. 
   
   
     9. The method of  claim 1 , wherein forming the dummy gate electrode and the dummy gate upper insulation layer comprise performing a chemical vapor deposition process. 
   
   
     10. The method of  claim 1 , wherein forming the dummy gate electrode and the dummy gate upper insulation layer comprises forming the dummy gate electrode and the dummy gate insulation layer to a thickness of 1000 Å to 4000 Å. 
   
   
     11. The method of  claim 2 , wherein ion-implanting first impurities to form first impurity regions comprises ion-implanting N-type impurities in the cell region and implanting N-type impurities in the core/perimeter region. 
   
   
     12. The method of  claim 11 , wherein ion-implanting N-type impurities comprises ion-implanting impurities selected from the group consisting of P and As. 
   
   
     13. The method of  claim 2 , wherein ion-implanting first impurities to form first impurity regions comprises ion-implanting N-type impurities in the cell region and ion-implanting P-type impurities in the core/perimeter region. 
   
   
     14. The method of  claim 13 , wherein ion-implanting N-type impurities comprises ion-implanting impurities selected from the group consisting of P and As; and wherein ion-implanting P-type impurities comprises ion-implanting impurities selected from the group consisting of B and BF 2 . 
   
   
     15. The method of  claim 1 , wherein ion-implanting first impurities to form first impurity regions comprises ion-implanting the first impurities into the semiconductor substrate at an energy of about 20 KeV. 
   
   
     16. The method of  claim 1 , wherein ion-implanting first impurities to form first impurity regions comprises ion-implanting first impurities to a density of about 1×10 16  atoms/cm 3 . 
   
   
     17. The method of  claim 1 , wherein ion-implanting first impurities to form first impurity regions comprises ion-implanting first impurities to a depth of about 1000 Å to 2000 Å from a surface of the semiconductor substrate. 
   
   
     18. The method of  claim 1 , further comprising annealing the semiconductor substrate after forming the first impurity regions. 
   
   
     19. The method of  claim 1 , further comprising, after forming the first impurity regions, ion-implanting second impurities to form a channel stop layer that invades a portion of the gate region. 
   
   
     20. The method of  claim 19 , wherein ion-implanting the second impurities to form the the channel stop layer comprises ion-implanting the second impurities at an energy of about 50 KeV. 
   
   
     21. The method of  claim 19 , wherein ion-implanting the second impurities to form the channel stop layer comprises ion-implanting the second impurities below 2000 Å from the surface of semiconductor substrate. 
   
   
     22. The method of  claim 1 , wherein forming spacers comprises forming a layer chosen selected from the group consisting of a silicon nitride layer or a silicon oxide nitride layer. 
   
   
     23. The method of  claim 1 , wherein forming spacers comprises forming spacers on the dummy gate upper insulation layer. 
   
   
     24. The method of  claim 1 , wherein ion-implanting first impurities to form second impurity regions comprises ion-implanting first impurities into the semiconductor substrate at an energy of about 50 KeV. 
   
   
     25. The method of  claim 1 , wherein ion-implanting first impurities to form second impurity regions comprises ion-implanting second impurities to a density of about 1×10 19  atoms/cm 3 . 
   
   
     26. The method of  claim 1 , wherein ion-implanting first impurities to form second impurity regions comprises ion-implanting first impurities to a depth under 2000 Å from a surface of semiconductor substrate. 
   
   
     27. The method of  claim 2 , wherein ion-implanting first impurities to form second impurity regions comprises:
 forming an interlayer insulation layer on a face of the semiconductor substrate; 
 flattening the interlayer insulation layer; and 
 removing the interlayer insulation layer formed in the cell region and forming the second impurity region in the cell region. 
 
   
   
     28. The method of  claim 27 , further comprising removing the dummy gate oxide layer on the source/drain region of the cell region. 
   
   
     29. The method of  claim 27 , wherein the interlayer insulation layer is formed of silicon nitride. 
   
   
     30. The method of  claim 27 , wherein flattening the interlayer insulation layer comprises a chemical mechanical polishing (CMP) or an etch-back. 
   
   
     31. The method of  claim 1 , wherein ion-implanting first impurities to form second impurity regions comprises ion-implanting first impurities through a self-alignment method in which the dummy gate upper insulation layer and the spacer are used as an ion implantation mask. 
   
   
     32. The method of  claim 1 , wherein depositing pad polysilicon layers comprises chemical vapor deposition of the pad polysilicon layers. 
   
   
     33. The method of  claim 1 , wherein depositing pad polysilicon layers comprises adding a conductive impurity to the pad polysilicon layers. 
   
   
     34. The method of  claim 1 , further comprising flattening the semiconductor substrate on which the pad polysilicon layer is formed with a chemical-mechanical polishing process to expose a portion of the dummy gate upper insulation layer or the spacer. 
   
   
     35. The method of  claim 1 , wherein removing the dummy gate upper insulation layer comprises anisotropically etching a portion of the dummy gate upper insulation layer from the dummy gate electrode. 
   
   
     36. The method of  claim 1 , wherein removing the dummy gate electrode comprises anisotropically etching the dummy gate electrode. 
   
   
     37. The method of  claim 1 , wherein removing the dummy gate electrode comprises dry etching the dummy gate electrode. 
   
   
     38. The method of  claim 1 , wherein annealing the semiconductor substrate comprises annealing at a temperature between about 800˜830° C. 
   
   
     39. The method of  claim 1 , wherein annealing the semiconductor substrate comprises annealing for at least one hour. 
   
   
     40. The method of  claim 1 , wherein ion-implanting second impurities to form third impurity regions comprises ion-implanting second impurities to a depth of about 500 Å to 1000 Å from the surface of semiconductor substrate. 
   
   
     41. The method of  claim 1 , wherein ion-implanting second impurities to form third impurity regions comprises ion-implanting second impurities into the semiconductor substrate at an energy of about 20 KeV. 
   
   
     42. The method of  claim 1 , wherein ion-implanting second impurities to form third impurity regions comprises ion-implanting second impurities to a density of about 1×10 16  atoms/cm 3 . 
   
   
     43. The method of  claim 1 , wherein annealing the semiconductor substrate comprises annealing after forming third impurity regions. 
   
   
     44. The method of  claim 1 , wherein forming the dummy gate oxide layer comprises thermally oxidizing the semiconductor substrate. 
   
   
     45. The method of  claim 44 , wherein thermally oxidizing comprises thermally oxidizing at about 800° C. 
   
   
     46. The method of  claim 1 , wherein forming the gate electrode comprises forming the gate electrode of polycrystalline silicon. 
   
   
     47. The method of  claim 46 , wherein forming the gate electrode of polycrystalline silicon comprises forming the gate electrode of polycrystalline silicon that contains a conductive impurity. 
   
   
     48. The method of  claim 1 , wherein forming the gate electrode comprises forming the gate electrode to a thickness of about 500 Å to 2000 Å. 
   
   
     49. The method of  claim 1 , further comprising, after forming the gate electrode:
 forming a conductive metal layer on the semiconductor substrate where the gate electrode is formed; 
 flattening the conductive metal layer with a chemical-mechanical polishing process until the pad polysilicon layers are exposed; and 
 isolating the gate electrode from the pad polysilicon layers by etching the gate electrode. 
 
   
   
     50. A method of manufacturing a transistor, comprising:
 depositing a device isolation film on a semiconductor substrate to define an active region; 
 sequentially depositing a dummy gate oxide layer, a dummy gate electrode, and a dummy gate upper insulation layer on the semiconductor substrate; 
 ion-implanting a first conductive impurity to form first impurity regions, the first impurity regions disposed in source/drain regions provided on both sides of the dummy gate electrode; 
 forming a spacer on a sidewall of the dummy gate electrode; 
 ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions by using the spacer as an ion implantation mask; 
 removing the dummy gate oxide layer from the source/drain regions; 
 forming self-aligned pad polysilicon layers that are defined by the spacer on the source/drain regions of the semiconductor substrate; 
 sequentially removing the dummy gate upper insulation layer and the dummy gate electrode; 
 annealing the semiconductor substrate; 
 locally ion-implanting a second conductive impurity into a gate region of the semiconductor substrate to form a third impurity region, the second conductive impurity having an impurity type opposite that of the first conductive impurity; and 
 removing the dummy gate oxide layer; 
 forming a gate insulation layer; and 
 forming a gate electrode on the gate region. 
 
   
   
     51. A method of manufacturing a transistor, comprising:
 forming a device isolation film on a semiconductor substrate; 
 accumulating a dummy gate oxide layer and a sacrificial oxide layer on the semiconductor substrate on which the device isolation film is formed; 
 patterning the sacrificial oxide layer and forming a dummy gate electrode on the semiconductor substrate on which the sacrificial oxide layer is formed; 
 flattening the semiconductor substrate on which the dummy gate electrode is formed; 
 removing the sacrificial oxide layer; 
 ion-implanting a first conductive impurity to form first impurity regions, the first impurity region disposed in source/drain regions provided on both sides of the dummy gate electrode; 
 forming a spacer on a sidewall of the dummy gate electrode; 
 ion-implanting the first conductive impurity to form second impurity regions that are overlapped by the first impurity regions by using the spacer as an ion implantation mask; 
 removing the dummy gate oxide layer from the source/drain regions; 
 forming a pad polysilicon layer on the semiconductor substrate; 
 flattening the pad polysilicon layer to expose the dummy gate electrode; 
 removing the dummy gate electrode; 
 annealing the semiconductor substrate; 
 locally ion-implanting a second conductive impurity into a gate region of the semiconductor substrate to form a third impurity region, the second conductive impurity having a conductivity type opposite that of the first conductive impurity; and 
 removing the dummy gate oxide layer; 
 forming a gate insulation layer; and 
 forming a gate electrode on the gate region.