PMOS transistor with compressive dielectric capping layer

Abstract

A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the post-treatment plasma. Processes of depositing a dielectric sublayer and post-treating the sublayer in plasma are repeated until a desired thickness is achieved. The resulting dielectric layer has residual compressive stress.

1. A PMOS transistor, comprising:
 a PMOS transistor structure on a substrate comprising a gate, p-doped source and drain regions on either side of said gate, and a channel underlying said gate; 
 a salicide layer covering said source and drain regions; and 
 a dielectric capping layer covering said salicide layer, said dielectric capping layer formed by steps comprising: 
 (a) providing in a vacuum chamber a deposition reactant mixture comprising A1 atoms of a chemical element A1 and A2 atoms of a chemical element A2, wherein said element A2 is more electronegative than said element A1, and wherein said A1 atoms have a positive oxidation state and said A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms; 
 (b) applying high-frequency (HF) and low-frequency (LF) power to said deposition reactant mixture to generate a deposition plasma containing excited A1-species and excited A2-species; 
 (c) depositing a dielectric sublayer on said substrate using said deposition plasma, said dielectric sublayer covering said salicide layer; 
 (d) providing a post-treatment gas containing peening species to a vacuum chamber, said post-treatment gas being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; 
 (e) applying HF and LF power to said post-treatment gas to generate a post-treatment plasma, said post-treatment plasma comprising excited peening species, and said post-treatment plasma being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; 
 (f) post-treating said dielectric sublayer in said post-treatment plasma; and 
 (g) repeating said steps (c) and (f) of depositing a dielectric sublayer and post-treating said dielectric sublayer until a desired thickness of dielectric material is achieved to form said dielectric capping layer. 
 
   
   
     2. A PMOS transistor as in  claim 1  wherein said applying HF and LF power to said deposition reactant mixture comprises applying LF power greater than said HF power. 
   
   
     3. A PMOS transistor as in  claim 1  wherein said applying HF and LF power to said post-treatment gas comprises applying LF power greater than said HF power. 
   
   
     4. A PMOS transistor as in  claim 1  wherein said A1 element is selected from a group consisting of silicon (Si), boron (B), and carbon (C), and said A2 element is selected from a group consisting of nitrogen (N), carbon (C), and oxygen (O). 
   
   
     5. A PMOS transistor as in  claim 4  wherein said dielectric material comprises a dielectric material selected from the group consisting of silicon nitride, silicon carbide, nitrogen-doped silicon carbide, boron nitride, silicon boron nitride, boron carbide, silicon boron carbide, carbon nitride, silicon oxide, and oxygen-doped silicon carbide. 
   
   
     6. A PMOS transistor as in  claim 1  wherein said providing a deposition reactant mixture further comprises:
 providing an inert gas in said vacuum chamber. 
 
   
   
     7. A PMOS transistor as in  claim 1  wherein said providing a deposition reactant mixture further comprises:
 providing peening species in said vacuum chamber. 
 
   
   
     8. A PMOS transistor as in  claim 1  wherein said providing a deposition reactant mixture comprises:
 flowing into said vacuum chamber a silicon-containing species and a nitrogen-containing species. 
 
   
   
     9. A PMOS transistor as in  claim 8  wherein said providing a deposition reactant mixture comprises:
 flowing a silicon-containing species selected from the group consisting of tetramethylsilane, tetraethylsilane, and silane. 
 
   
   
     10. A PMOS transistor as in  claim 8  wherein said providing a deposition reactant mixture comprises:
 flowing ammonia (NH 3 ) into said vacuum chamber. 
 
   
   
     11. A PMOS transistor as in  claim 8  wherein said providing a post-treatment gas containing peening species comprises:
 flowing ammonia (NH 3 ). 
 
   
   
     12. A PMOS transistor as in  claim 1  wherein said providing a post-treatment gas containing peening species comprises:
 providing a post-treatment gas containing hydrogen atoms. 
 
   
   
     13. A PMOS transistor as in  claim 1  wherein said providing a post-treatment gas containing peening species comprises:
 providing a post-treatment gas containing A2 atoms and not containing A1 atoms. 
 
   
   
     14. A PMOS transistor as in  claim 1  wherein said providing a post-treatment gas containing peening species comprises:
 providing a post-treatment gas containing A1 atoms and not containing A2 atoms. 
 
   
   
     15. A PMOS transistor as in  claim 1  wherein said providing a post-treatment gas further comprises:
 providing an inert gas in said vacuum chamber. 
 
   
   
     16. A PMOS transistor as in  claim 1  wherein said repeating said steps (c) and (f) of depositing a dielectric sublayer and post-treating said dielectric sublayer comprises:
 repeating said processes to form a plurality of dielectric sublayers on said substrate, said plurality being in a range of about from 12 to 40 dielectric sublayers. 
 
   
   
     17. A PMOS transistor as in  claim 1  wherein said post-treating said dielectric sublayer in said post-treatment plasma comprises:
 exposing said dielectric sublayer to said post-treatment plasma for a sublayer post-treatment time in a range of about from 0.5 second to 10 seconds. 
 
   
   
     18. A PMOS transistor as in  claim 1  wherein said depositing a dielectric sublayer comprises:
 depositing a dielectric sublayer having a thickness in a range of about from 0.5 nm to 20 nm. 
 
   
   
     19. A PMOS transistor as in  claim 1  wherein:
 said depositing a dielectric sublayer in step (c) comprises depositing a dielectric sublayer directly on said salicide layer; and 
 said repeating said steps (c) and (f) of depositing a dielectric sublayer and post-treating said dielectric sublayer forms a dielectric capping layer directly on said salicide layer. 
 
   
   
     20. A PMOS transistor as in  claim 1  wherein:
 said dielectric capping layer has compressive stress. 
 
   
   
     21. A PMOS transistor, comprising:
 a PMOS transistor structure on a substrate comprising a gate, p-doped source and drain regions on either side of said gate, and a channel underlying said gate; 
 a salicide layer covering said source and drain regions; and 
 a dielectric capping layer having compressive stress covering said salicide layer, said dielectric capping layer formed by steps comprising: 
 (a) providing in a vacuum chamber a deposition reactant mixture comprising A1 atoms of a chemical element A1 and A2 atoms of a chemical element A2, wherein said element A2 is more electronegative than said element A1, and wherein said A1 atoms have a positive oxidation state and said A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms; 
 (b) applying high-frequency (HF) and low-frequency (LF) power to said deposition reactant mixture to generate a deposition plasma containing excited A1-species and excited A2-species; 
 (c) depositing a dielectric layer on said substrate using said deposition plasma, said dielectric layer covering said salicide layer; 
 (d) providing a post-treatment gas containing peening species to a vacuum chamber, said post-treatment gas being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; 
 (e) applying HF and LF power to said post-treatment gas to generate a post-treatment plasma, said post-treatment plasma comprising excited peening species, and said post-treatment plasma being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; and 
 (f) post-treating said dielectric layer in said post-treatment plasma to form said dielectric capping layer having compressive stress covering said salicide layer. 
 
   
   
     22. A PMOS transistor as in  claim 21  wherein:
 said depositing a dielectric layer in step (c) comprises depositing a dielectric layer directly on said salicide layer. 
 
   
   
     23. A transistor containing a dielectric layer and located on an integrated circuit substrate, said dielectric layer formed by steps comprising:
 (a) providing in a vacuum chamber a deposition reactant mixture comprising A1 atoms of a chemical element A1 and A2 atoms of a chemical element A2, wherein said element A2 is more electronegative than said element A1, and wherein said A1 atoms have a positive oxidation state and said A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms; 
 (b) applying high-frequency (HF) and low-frequency (LF) power to said deposition reactant mixture to generate a deposition plasma containing excited A1-species and excited A2-species; 
 (c) depositing a dielectric sublayer on said integrated circuit substrate using said deposition plasma; 
 (d) providing a post-treatment gas containing peening species to a vacuum chamber, said post-treatment gas being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; 
 (e) applying HF and LF power to said post-treatment gas to generate a post-treatment plasma, said post-treatment plasma comprising excited peening species, and said post-treatment plasma being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; 
 (f) post-treating said dielectric sublayer in said post-treatment plasma; and 
 (g) repeating said processes (c) and (f) of depositing a dielectric sublayer and post-treating said dielectric sublayer until a desired thickness of dielectric material is achieved. 
 
   
   
     24. A transistor containing a dielectric layer and located on an integrated circuit substrate, said dielectric layer formed by steps comprising:
 (a) providing in a vacuum chamber a deposition reactant mixture comprising A1 atoms of a chemical element A1 and A2 atoms of a chemical element A2, wherein said element A2 is more electronegative than said element A1, and wherein said A1 atoms have a positive oxidation state and said A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms; 
 (b) applying high-frequency (HF) and low-frequency (LF) power to said deposition reactant mixture to generate a deposition plasma containing excited A1-species and excited A2-species; 
 (c) depositing a dielectric layer on said integrated circuit substrate using said deposition plasma; 
 (d) providing a post-treatment gas containing peening species to a vacuum chamber, said post-treatment gas being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; 
 (e) applying HF and LF power to said post-treatment gas to generate a post-treatment plasma, said post-treatment plasma comprising excited peening species, and said post-treatment plasma being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; and 
 post-treating said dielectric layer in said post-treatment plasma.