Jitter measuring apparatus, jitter measuring method and PLL circuit

Abstract

A jitter measurement apparatus for measuring an intrinsic jitter of a circuit to be tested including a phase detector which outputs a signal according to a phase difference between a supplied first input signal and a supplied second input signal, includes: an input unit for supplying an identical signal to the phase detector as the first input signal and as the second input signal; and a jitter measurement unit for measuring the intrinsic jitter of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested according to an signal output from the phase detector.

1. A jitter measurement apparatus for measuring an intrinsic jitter of a circuit to be tested including a phase detector which outputs a signal according to a phase difference between a supplied first input signal and a supplied second input signal, comprising:
 an input unit for supplying an identical signal to said phase detector as the first input signal and as the second input signal; and 
 a jitter measurement unit for measuring the intrinsic jitter which is generated in an inside of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested according to a signal output from said phase detector, 
 wherein the intrinsic jitter is measured in a state of no jitter derived from the input signals being included in the output signal of the phase detector by supplying the identical signal as the first input signal and as the second input signals, 
 wherein the circuit to be tested comprises a latter circuit which receives a signal output from said phase detector and outputs a signal based on a received signal, 
 wherein said jitter measurement apparatus measures a jitter of a signal output from said latter circuit, and 
 wherein said jitter measurement unit measures an intrinsic jitter of said latter circuit based on a difference between a jitter of a signal output from said phase detector and a jitter of a signal output from said latter circuit. 
 
   
   
     2. The jitter measurement apparatus in  claim 1 , wherein said jitter measurement unit measures the intrinsic jitter of said phase detector by measuring a jitter of a signal output from said phase detector. 
   
   
     3. The jitter measurement apparatus in  claim 1 , wherein said circuit to be tested corresponding to a phase locked loop circuit further comprises a latter circuit comprising:
 a charge pump for outputting a signal according to a signal output from said phase detector; 
 a loop filter for outputting a signal according to a signal output from said charge pump; 
 a voltage controlled oscillator for outputting an oscillation signal according to a signal output from said loop filter; and 
 a frequency divider for dividing the oscillation signal output from said voltage controlled oscillator and outputting a divided signal to said phase detector, and 
 said jitter measurement unit measures at least one of the signal output from said charge pump, said loop filter, said voltage controlled oscillator and said frequency divider. 
 
   
   
     4. The jitter measurement apparatus in  claim 3 , wherein said input unit further comprises:
 a signal selector which receives the second input signal and a signal output from said frequency divider, wherein said signal selector selects the second input signal and inputs the selected second input signal to said phase detector when measuring an intrinsic jitter of said circuit to be tested, and said signal selector selects a signal output from said frequency divider and inputs the selected signal outputted from said frequency divider to said phase detector when said circuit to be tested operates as a PLL circuit. 
 
   
   
     5. The jitter measurement apparatus in  claim 4 , wherein said input unit further comprises a dummy selector which receives the first input signal and inputs the received first input signal to said phase detector, said dummy selector having the same characteristic of said signal selector. 
   
   
     6. The jitter measurement apparatus in  claim 1 , wherein said input unit inputs signals, between which the phase difference is approximately zero and whose wave shapes are identical, to said phase detector as the first input signal and the second input signal. 
   
   
     7. The jitter measurement apparatus in  claim 1 , wherein said input unit inputs signals, between which the phase difference is not zero and whose wave shapes are identical, to said phase detector as the first input signal and the second input signal. 
   
   
     8. The jitter measurement apparatus in  claim 1 , wherein said input section inputs a clock signal, whose period is constant, to said phase detector as the first input signal and as the second input signal. 
   
   
     9. The jitter measurement apparatus in  claim 1 , wherein said input section inputs a data signal whose period is not constant, to said phase detector as the first input signal and as the second input signal. 
   
   
     10. The jitter measurement apparatus in  claim 1 , wherein
 said input section changes a frequency of each of the first input signal and the second input signal sequentially and inputs the changed signals to said phase detector, and 
 said jitter measurement unit measures the intrinsic jitter of said circuit to be tested every time said input unit changes the frequency. 
 
   
   
     11. A phase locked loop circuit comprising an oscillation mode for inputting an oscillation signal synchronized with a reference clock that is supplied, and a measuring mode for measuring an intrinsic jitter which is generated in an inside of the phase locked loop circuit, comprising:
 a voltage controlled oscillator for generating the oscillation signal having a frequency based on a control voltage; 
 a frequency divider for dividing the oscillation signal; 
 a phase detector for generating the control voltage based on a phase difference between the reference clock and a comparable signal that is supplied; and 
 a signal selector which receives the reference clock and a signal output from said frequency divider, 
 wherein said signal selector supplies the reference clock to said phase detector as the comparable signal when said phase locked loop circuit operates in the measurement mode, and said signal selector supplies a signal output from said frequency divider to said phase detector as the comparable signal when said phase locked loop circuit operates in the oscillation mode, 
 wherein the intrinsic jitter is measured in a state of no jitter derived from the input signals being included in the output signal of the phase detector by supplying the identical signal as the first input signal and as the second input signals, 
 wherein the phase locked loop circuit comprises a latter circuit which receives a signal output from said phase detector and outputs a signal based on a received signal, 
 wherein a jitter of a signal output from said latter circuit is measured, and 
 wherein an intrinsic jitter of said latter circuit is measured based on a difference between a jitter of a signal output from said phase detector and a jitter of a signal output from said latter circuit. 
 
   
   
     12. The phase locked loop circuit in  claim 11 , further comprising an output terminal from which the control voltage of said phase detector is output to an external measurement apparatus. 
   
   
     13. A method for measuring an intrinsic jitter of a circuit to be tested comprising a phase detector which outputs a signal based on a phase difference between a supplied first input signal and a supplied second input signal, comprising steps of:
 supplying an identical signal to said phase detector as the first input signal and as the second input signal; and 
 measuring the intrinsic jitter which is generated in an inside of the circuit to be tested by measuring a jitter of a signal which is generated in an inside of the circuit to be tested, according to an output signal output from said phase detector, 
 wherein the intrinsic jitter is measured in a state of no jitter derived from the input signals being included in the output signal of the phase detector by supplying the identical signal as the first input signal and as the second input signals, 
 wherein a jitter of a signal output from a latter circuit that receives a signal output from said phase detector and outputs a signal based on a received signal is measured, 
 wherein the circuit to be tested comprises the latter circuit, and 
 wherein an intrinsic jitter of said latter circuit is measured based on a difference between a jitter of a signal output from said phase detector and a jitter of a signal output from said latter circuit. 
 
   
   
     14. The jitter measurement apparatus in  claim 1 , wherein said circuit to be tested corresponding to a phase locked loop circuit further comprises a latter circuit comprising:
 a charge pump for outputting a signal according to a signal output from said phase detector; 
 a loop filter for outputting a signal according to a signal output from said charge pump; 
 a voltage controlled oscillator for outputting an oscillation signal according to a signal output from said loop filter; and 
 a frequency divider for dividing the oscillation signal output from said voltage controlled oscillator and outputting a divided signal to said phase detector, and 
 said jitter measurement unit measures at least one of the signal output from said charge pump, said loop filter, said voltage controlled oscillator and said frequency divider. 
 
   
   
     15. The jitter measurement apparatus in  claim 1 , wherein said jitter measurement unit measures an intrinsic jitter of said latter circuit comparing the jitter of the signal output from said phase detector with the jitter of the signal output from said latter circuit.