Method of manufacturing semiconductor device having transition metal oxide layer and related device

Abstract

Provided is a method of manufacturing a semiconductor device having a switching device capable of preventing a snake current. First, a transition metal oxide layer and a leakage control layer are alternately stacked on a substrate 1 to 20 times to form a varistor layer. The transition metal oxide layer is formed to contain an excessive transition metal compared to its stable state. The leakage control layer may be formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer.

1. A method of forming a semiconductor device, comprising:
 stacking a transition metal oxide layer and a leakage control layer on a substrate to form a varistor layer, wherein the transition metal oxide layer contains an excessive transition metal compared to its stable state; 
 forming a lower interconnection electrically connected to a lower end of the varistor layer; and 
 forming an intermediate interconnection electrically connected to an upper end of the varistor layer. 
 
     
     
       2. The method of  claim 1 , further comprising forming a data storage element between the varistor layer and the intermediate interconnection. 
     
     
       3. The method of  claim 2 , further comprising:
 forming a first electrode between the lower interconnection and the varistor layer; and 
 forming a second electrode between the varistor layer and the data storage element. 
 
     
     
       4. The method of  claim 3 , wherein the first electrode is formed of one selected from the group consisting of an iridium (Ir) layer, a platinum (Pt) layer, a nickel (Ni) layer, a ruthenium (Ru) layer, a palladium (Pd) layer, a gold (Au) layer, a silver (Ag) layer, a copper (Cu) layer, and a cobalt (Co) layer. 
     
     
       5. The method of  claim 3 , wherein the second electrode is formed of one selected from the group consisting of an iridium (Ir) layer, a platinum (Pt) layer, a nickel (Ni) layer, a ruthenium (Ru) layer, a palladium (Pd) layer, a gold (Au) layer, a silver (Ag) layer, a copper (Cu) layer, and a cobalt (Co) layer. 
     
     
       6. The method of  claim 3 , wherein the first electrode and the second electrode are formed of the same material. 
     
     
       7. The method of  claim 2 , wherein the data storage element is formed of one selected from the group consisting of a variable resistance layer, a phase-change material layer, a polymer pattern, a magnetic tunnel junction (MTJ), and a ferroelectric pattern. 
     
     
       8. The method of  claim 7 , wherein the variable resistance layer is formed of a transition metal oxide layer having a different composition ratio from the varistor layer. 
     
     
       9. The method of  claim 2 , further comprising:
 forming an upper varistor layer on the intermediate interconnection; 
 forming an upper data storage element on the upper varistor layer; and 
 forming an upper interconnection on the upper data storage element. 
 
     
     
       10. The method of  claim 9 , wherein forming the upper varistor layer comprises alternately stacking the transition metal oxide layer and the leakage control layer on the intermediate interconnection 1 to 20 times. 
     
     
       11. The method of  claim 1 , wherein the transition metal oxide layer is formed of one selected from the group consisting of a TiO layer, a NbO layer, a NiO layer, a ZnO layer, a HfO layer, a YO layer, a VO layer, a CrO layer, a MoO layer, a WO layer, and a ZrO layer. 
     
     
       12. The method of  claim 1 , wherein the transition metal oxide layer is formed of a material, in which one selected from the group consisting of Ir, Pt, Ru, Ni, Pd, Au, Ag, and Co, is added to one selected from the group consisting of a TiO layer, a NbO layer, a NiO layer, a ZnO layer, a HfO layer, a YO layer, a VO layer, a CrO layer, a MoO layer, a WO layer, and a ZrO layer. 
     
     
       13. The method of  claim 1 , wherein the leakage control layer is formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer. 
     
     
       14. The method of  claim 1 , wherein the varistor layer is formed by alternately stacking the transition metal oxide layer and the leakage control layer 1 to 20 times. 
     
     
       15. A semiconductor device comprising:
 a substrate; 
 a varistor disposed on the substrate and having a transition metal oxide pattern and a leakage control pattern, wherein the transition metal oxide pattern contains an excessive transition metal compared to its stable state; 
 a lower interconnection electrically connected to a lower end of the varistor; and 
 an intermediate interconnection crossing the lower interconnection and electrically connected to an upper end of the varistor. 
 
     
     
       16. The device of  claim 15 , further comprising a data storage element disposed between the varistor and the intermediate interconnection. 
     
     
       17. The device of  claim 16 , further comprising:
 a first electrode disposed between the lower interconnection and the varistor; and 
 a second electrode disposed between the varistor and the data storage element. 
 
     
     
       18. The device of  claim 17 , wherein the first electrode and the second electrode are formed of the same material. 
     
     
       19. The device of  claim 16 , wherein the data storage element is formed of one selected from the group consisting of a variable resistance layer, a phase-change material layer, a polymer pattern, a magnetic tunnel junction (MTJ), and a ferroelectric pattern. 
     
     
       20. The device of  claim 16 , further comprising:
 an upper interconnection crossing over the intermediate interconnection; 
 an upper varistor disposed between the intermediate interconnection and the upper interconnection; and 
 an upper data storage element disposed between the upper varistor and the upper interconnection. 
 
     
     
       21. The device of  claim 20 , wherein the upper varistor is formed by alternately stacking the transition metal oxide pattern and the leakage control pattern 1 to 20 times. 
     
     
       22. The device of  claim 20 , further comprising:
 a third electrode disposed between the intermediate interconnection and the upper varistor; and 
 a fourth electrode disposed between the upper varistor and the upper data storage element. 
 
     
     
       23. The device of  claim 22 , wherein the third electrode and the fourth electrode are formed of the same material. 
     
     
       24. The device of  claim 15 , wherein the transition metal oxide pattern is formed of one selected from the group consisting of a TiO layer, a NbO layer, a NiO layer, a ZnO layer, a HfO layer, a YO layer, a VO layer, a CrO layer, a MoO layer, a WO layer, and a ZrO layer. 
     
     
       25. The device of  claim 15 , wherein the transition metal oxide pattern is formed of a material, in which one selected from the group consisting of Ir, Pt, Ru, Ni, Pd, Au, Ag, and Co, is added to one selected from the group consisting of a TiO layer, a NbO layer, a NiO layer, a ZnO layer, a HfO layer, a YO layer, a VO layer, a CrO layer, a MoO layer, a WO layer, and a ZrO layer. 
     
     
       26. The device of  claim 15 , wherein the leakage control pattern is formed of one selected from the group consisting of a Mg layer, a Ta layer, an Al layer, a Zr layer, a Hf layer, a polysilicon layer, a conductive carbon group layer, and a Nb layer. 
     
     
       27. The device of  claim 15 , wherein the varistor is formed by alternately stacking the transition metal oxide pattern and the leakage control pattern 1 to 20 times.