Access device having vertical channel and related semiconductor device and a method of fabricating the access device

Abstract

An access device and a semiconductor device are disclosed. The access device includes a vertically oriented channel separating a lower source/drain region and an upper source/drain region, a gate dielectric disposed on the channel, and a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line comprises a descending lip portion disposed proximate to the gate dielectric and overlaying at least a portion of the lower source/drain region.

1. An access device adapted for use in a semiconductor device and comprising:
 a vertically oriented channel separating a lower source/drain region and an upper source/drain region; 
 a gate dielectric disposed on the channel; 
 a unified gate electrode/connection line coupled to the channel across the gate dielectric, wherein the unified gate electrode/connection line is formed on a first interlayer insulating layer and over the lower source/drain region, and comprises;
 a descending lip portion having a vertical edge disposed directly on the gate dielectric, and a lower lateral edge extending from the vertical edge away from the channel to overlay at least a portion of the lower source/drain region, and 
 a lateral portion extending laterally from the descending lip portion away from the channel and having a flat lateral lower surface disposed on the interlayer insulating layer, 
 
 wherein an upper surface of the lower source/drain region is lower than an upper surface of the first interlayer insulating layer. 
 
     
     
       2. The access device of  claim 1 , wherein the gate dielectric comprises a lower lateral portion extending away from the channel and separating the descending lip portion of the unified gate electrode/connection line from the lower source/drain region. 
     
     
       3. The access device of  claim 1 , wherein the unified gate electrode/connection line is a unified gate electrode/word line and the lower source/drain region is associated with a buried bit line (BBL) structure. 
     
     
       4. The access device of  claim 3 , wherein the BBL structure comprises an offset step region. 
     
     
       5. The access device of  claim 4 , wherein the lower source/drain region is a multi-level source/drain region comprising a first source/drain region disposed in an upper portion of the offset step region and a second source/drain region disposed in a lower portion of the offset step region. 
     
     
       6. The access device of  claim 3 , wherein the lower source/drain region comprises a first source/drain region disposed in a peripheral region at least partially surrounding a portion of the channel and a second source/drain region disposed in a lateral region extending the length of the BBL structure. 
     
     
       7. The access device of  claim 6 , further comprising a contact pad electrically connected to the upper source/drain region. 
     
     
       8. The access device of  claim 7 , wherein the channel comprises a vertical pillar of silicon material and the contact pad is a silicon contact pad epitaxially grown from the silicon material. 
     
     
       9. The access device of  claim 1 , wherein the unified gate electrode/connection line is a unified gate electrode/word line and the lower source/drain region is associated with a buried bit line (BBL) structure; and
 wherein the unified gate electrode/word line, the channel, the lower source/drain region and the upper source region operate in combination as a field effect transistor (FET) within a memory cell. 
 
     
     
       10. The access device of  claim 1  wherein the unified gate electrode/connection line completely surrounds at least a portion of the channel. 
     
     
       11. A semiconductor device, comprising:
 adjacent first and second access devices disposed on a substrate, the first access device comprising a vertically oriented first channel separating a first lower source/drain region and a first upper source/drain region and a first gate dielectric disposed on the first channel, and the second access device comprising a vertically oriented second channel separating a second lower source/drain region and a second upper source/drain region and a second gate dielectric disposed on the second channel; 
 a first interlayer insulating layer disposed on the substrate and separating the first and second access devices; and 
 a unified gate electrode/connection line disposed on the first interlayer insulating layer and respectively coupled to the first and second channels of the first and second access devices, wherein the unified gate electrode/connection line comprises opposing first and second descending lip portions separated by an intervening lateral portion, 
 wherein the first descending lip portion comprises a first vertical edge disposed directly on the first gate dielectric, and a first lower lateral edge extending laterally from the first vertical edge away from the first channel to overlay at least a portion of the first lower source/drain region, 
 the second descending lip portion comprises a second vertical edge disposed directly on the first gate dielectric, and a second lower lateral edge extending laterally from the second vertical edge away from the second channel to overlay at least a portion of the second lower source/drain region, 
 the lateral portion extends over a flat upper surface of the first interlayer insulating layer, and 
 the first and second lower lateral edges are lower than the flat upper surface of the first interlayer insulating layer. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the first gate dielectric comprises a first lower lateral portion extending away from the first access device and separating the first descending lip portion from the first lower source/drain region, and
 the second gate dielectric comprises a second lower lateral portion extending away from the second access device and separating the second descending lip portion from the second lower source/drain region. 
 
     
     
       13. The semiconductor device of  claim 11 , wherein the semiconductor device is a semiconductor memory device, the unified gate electrode/connection line is a unified gate electrode/word line, and the first and second source/drain regions are disposed in a respective buried bit line (BBL) structure. 
     
     
       14. The semiconductor access device of  claim 11 , wherein the first and second source/drain regions are each respective multi-level source/drain regions comprising one source/drain region formed in an upper portion of an offset step region and another source/drain region formed in a lower portion of an offset step region. 
     
     
       15. The semiconductor device of  claim 11 , wherein each of the first and second source/drain regions comprises one source/drain region formed in a peripheral region at least partially surrounding a portion of a corresponding one of the first and second channels and another source/drain region formed as a lateral region extending the length of a corresponding BBL structure. 
     
     
       16. The semiconductor device of  claim 11 , wherein the unified gate electrode/connection line is a unified gate electrode/word line and the first and second lower source/drain regions are respectively associated with a buried bit line (BBL) structure, and each one of the first and second access devices operates as a field effect transistor (FET) in a respective memory cell. 
     
     
       17. The semiconductor device of  claim 16 , wherein the semiconductor device is one selected from a group consisting of a dynamic random access memory (DRAM), a static random access memory (SRAM), a phase random access memory (PRAM), a NOR flash memory, and a NAND flash memory.