Damascene metal-insulator-metal (MIM) device with improved scaleability

Abstract

A present method of fabricating a memory device includes the steps of providing a dielectric layer, providing an opening in the dielectric layer, providing a first conductive body in the opening, providing a switching body in the opening, the first conductive body and switching body filling the opening, and providing a second conductive body over the switching body. In an alternate embodiment, a second dielectric layer is provided over the first-mentioned dielectric layer, and the switching body is provided in an opening in the second dielectric layer.

1. A method of fabricating a memory device comprising:
 providing a dielectric layer; 
 providing an opening in the dielectric layer; 
 depositing insulating walls in the opening in the dielectric layer, wherein the insulating walls are in direct contact with an entire depth of the opening; 
 depositing a first conductive body in the remaining opening; 
 thermally oxidizing a top portion of the first conductive body to form a switching body, wherein the first conductive body and the switching body filling the remaining opening, and wherein the first conductive body and the switching body are in direct contact with the insulating walls; and 
 providing a second conductive body over the switching body. 
 
     
     
       2. The method of  claim 1  wherein the second conductive body is provided by providing a conductive layer over the dielectric layer and switching body and patterning the conductive layer to form the second conductive body. 
     
     
       3. The method of  claim 1  wherein the second conductive body is provided by providing a second dielectric layer over first-mentioned dielectric layer and switching layer and switching body, providing an opening in the second dielectric layer, and providing the second conductive body in the opening in the second dielectric layer. 
     
     
       4. A method of fabricating a memory device comprising:
 providing a dielectric layer; 
 providing an opening in the dielectric layer; 
 depositing insulating walls in the opening in the dielectric layer, wherein the insulating walls are in direct contact with the opening; 
 depositing a first conductive body in the remaining opening in the dielectric layer, wherein a length of the first conductive body is in direct contact with the insulating walls; 
 thermally oxidizing a top portion of the first conductive body to form a switching body, wherein the first conductive body and switching body fill the remaining opening, and wherein the first conductive body and the switching body are in direct contact with the insulating walls; and 
 providing a second conductive body over the switching body. 
 
     
     
       5. The method of  claim 4  wherein the second conductive body is provided by providing a conductive layer over the dielectric layer and switching body and patterning the conductive layer to form the second conductive body. 
     
     
       6. The method of  claim 4  wherein the second conductive body is provided by providing a second dielectric layer over first-mentioned dielectric layer and switching layer and switching body, providing an opening in the second dielectric layer, and providing the second conductive body in the opening in the second dielectric layer. 
     
     
       7. A method of fabricating a memory device comprising:
 providing a dielectric layer; 
 providing an opening in the dielectric layer; 
 depositing insulating walls in the opening in the dielectric layer, wherein the insulating walls are in direct contact with an entire depth of the opening; 
 depositing a first conductive body in the remaining opening to fill the opening; 
 thermally oxidizing a top portion of the first conductive body to form a switching body, the first conductive body and switching body filling the remaining opening, wherein the first conductive body and the switching body are in direct contact with the insulating walls; and 
 providing a second conductive body over the switching body. 
 
     
     
       8. The method of  claim 7  wherein the second conductive body is provided by providing a conductive layer over the dielectric layer and switching body and patterning the conductive layer to form the second conductive body. 
     
     
       9. The method of  claim 7  wherein the second conductive body is provided by providing a second dielectric layer over first-mentioned dielectric layer and switching layer and switching body, providing an opening in the second dielectric layer, and providing the second conductive body in the opening in the second dielectric layer. 
     
     
       10. The method of  claim 1 , wherein a length of the first conductive body is in direct contact with the insulating walls. 
     
     
       11. The method of  claim 7 , wherein a length of the first conductive body is in direct contact with the insulating walls.