Programmable via devices in back end of line level

Abstract

Programmable via devices and methods for the fabrication thereof are provided. In one aspect, a programmable via device is provided. The programmable via device comprises a first dielectric layer; at least one isolation layer over the first dielectric layer; a heater within the isolation layer; a capping layer over a side of the isolation layer opposite the first dielectric layer; at least one programmable via extending through the capping layer and at least a portion of the isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; a conductive cap over the programmable via; a second dielectric layer over a side of the capping layer opposite the isolation layer; a first conductive via and a second conductive via, each extending through the second dielectric layer, the capping layer and at least a portion of the isolation layer and in contact with the heater; and a third conductive via extending through the second dielectric layer and in contact with the conductive cap.

1. A method of fabricating a programmable via device over a device layer of a semiconductor chip, the method comprising the steps of:
 depositing a first dielectric layer on the device layer; 
 depositing a first isolation layer over a side of the first dielectric layer opposite the device layer; 
 forming a heater on a side of the first isolation layer opposite the first dielectric layer; 
 depositing a second isolation layer over the side of the first isolation layer opposite the first dielectric layer so as to cover the heater; 
 forming a first conductive via and a second conductive via each extending through the second isolation layer and in contact with the heater; 
 depositing a capping layer over a side of the second isolation layer opposite the first isolation layer; 
 forming at least one programmable via extending through the capping layer and the second isolation layer and in contact with the heater, the programmable via comprising at least one phase change material; 
 forming a conductive cap over the programmable via; 
 depositing a second dielectric layer over a side of the capping layer opposite the second isolation layer; 
 extending each of the first conductive via and the second conductive via through the capping layer and through the second dielectric layer; and 
 forming a third conductive via extending through the second dielectric layer and in contact with the conductive cap. 
 
     
     
       2. The method of  claim 1 , wherein the step of forming the heater comprises the steps of:
 depositing a heater material layer on the side of the first isolation layer opposite the first dielectric layer; and 
 patterning the heater material layer to form the heater. 
 
     
     
       3. The method of  claim 2 , wherein the heater material layer is deposited on the side of the first isolation layer opposite the first dielectric layer using one or more of reactive sputtering, a chemical vapor deposition technique and atomic layer deposition, and wherein the heater material layer is patterned using reactive ion etching. 
     
     
       4. The method of  claim 1 , wherein the second isolation layer is deposited over the side of the first isolation layer opposite the first dielectric layer so as to cover the heater using low pressure chemical vapor deposition or plasma enhanced chemical vapor deposition. 
     
     
       5. The method of  claim 1 , wherein the step of forming the first conductive via and the second conductive via comprises the steps of:
 etching a first via and a second via each extending through the second isolation layer; and 
 filling the first via and the second via with at least one metal such that the metal makes contact with the heater. 
 
     
     
       6. The method of  claim 5 , wherein the first via and the second via are etched using reactive ion etching. 
     
     
       7. The method of  claim 5 , wherein the metal comprises one or more of tungsten, tantalum, tantalum nitride, titanium, titanium nitride and copper. 
     
     
       8. The method of  claim 1 , wherein the step of forming the conductive cap over the programmable via comprises the steps of:
 depositing a conductive capping layer over a side of the capping layer opposite the second isolation layer; and 
 patterning the conductive capping layer to form the conductive cap over the programmable via. 
 
     
     
       9. The method of  claim 8 , wherein the conductive capping layer is patterned using reactive ion etching. 
     
     
       10. The method of  claim 1 , wherein the step of forming the third conductive via comprises the steps of:
 etching a third via extending through the second dielectric layer; and 
 filling the third via with at least one metal. 
 
     
     
       11. The method of  claim 10 , wherein the third via is etched using reactive ion etching. 
     
     
       12. The method of  claim 10 , wherein the metal comprises one or more of tungsten, tantalum, tantalum nitride, titanium, titanium nitride and copper.