Interconnect structures, methods for fabricating interconnect structures, and design structures for a radiofrequency integrated circuit

Abstract

Interconnect structures that include a passive element, such as a thin film resistor or a metal-insulator-metal (MIM) capacitor, methods for fabricating an interconnect structure that includes a passive element, and design structures embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, such as a radiofrequency integrated circuit. A top surface of a dielectric layer is recessed relative to a top surface of a conductive feature in the dielectric layer. The passive element is formed on the recessed top surface of the dielectric layer and includes a layer of a conductive material that is coplanar with, or below, the top surface of the conductive feature.

1. A method for fabricating a back-end-of-line (BEOL) interconnect structure and a passive element, the method comprising:
 forming a first conductive feature extending through a dielectric layer of a metallization level of the BEOL interconnect structure; 
 in the absence of a mask layer on a top surface of the dielectric layer, recessing the top surface of the dielectric layer relative to a top surface of the first conductive feature; 
 after the top surface of the dielectric layer is recessed, depositing a conductive material layer on the recessed top surface of the dielectric layer; 
 forming a patterned photoresist layer on the conductive material layer; and 
 selectively etching the conductive material layer in the presence of the patterned photoresist layer to form a portion of the passive element that has a top surface that is approximately coplanar with the top surface of the first conductive feature or below the top surface of the first conductive feature. 
 
     
     
       2. The method of  claim 1  wherein the dielectric layer is comprised of a dielectric material and the first conductive feature is comprised of a conductor, and recessing the top surface of the dielectric layer comprises:
 performing a reactive ion etching process to at least partially remove the dielectric material of the dielectric layer at a significantly higher rate than the conductor of the first conductive feature. 
 
     
     
       3. The method of  claim 1  wherein the dielectric layer is comprised of a dielectric material and the first conductive feature is comprised of a conductor, and recessing the top surface of the dielectric layer comprises:
 exposing the dielectric layer to a wet chemical isotropic etchant to at least partially remove the dielectric material of the dielectric layer at a significantly higher rate than the first conductive feature. 
 
     
     
       4. The method of  claim 1  wherein the dielectric layer is comprised of a dielectric material and the first conductive feature is comprised of a conductor, and recessing the top surface of the dielectric layer comprises:
 exposing the top surface of the dielectric layer to a plasma to generate a damaged thickness extending from the top surface into the dielectric layer; and 
 removing the damaged thickness with an etching process that etches the dielectric material in the damaged thickness of the dielectric layer at a significantly higher rate than the conductor of the conductive feature. 
 
     
     
       5. The method of  claim 1  wherein the passive element is a resistor, and the portion of the passive element is a body of the resistor. 
     
     
       6. The method of  claim 1  wherein the passive element is a capacitor, and the portion of the passive element is an electrode of the capacitor. 
     
     
       7. The method of  claim 1  wherein the top surface of the portion of the passive element is located below the top surface of the first conductive feature. 
     
     
       8. The method of  claim 1  further comprising:
 forming a second conductive feature extending through the dielectric layer, 
 wherein a recess is formed between the first and second conductive features when the top surface of the dielectric layer is recessed. 
 
     
     
       9. The method of  claim 8  wherein the portion of the passive element is laterally positioned in the recess between the first and second conductive features, and further comprising:
 before the conductive material layer is etched to form the portion of the passive element, masking a corresponding portion of the conductive material layer that is laterally positioned in the recess between the first and second conductive features. 
 
     
     
       10. A method for fabricating a back-end-of-line (BEOL) interconnect structure and a passive element, the method comprising:
 forming a first conductive feature extending through a layer stack of first and second dielectric layers in a metallization level; 
 removing the first dielectric layer from the second dielectric layer to expose a top surface of the second dielectric layer so that the top surface of the second dielectric layer has a recessed relationship relative to a top surface of the first conductive feature; 
 after the first dielectric layer is removed, depositing a conductive material layer on the top surface of the second dielectric layer; 
 forming a patterned photoresist layer on the conductive material layer; and 
 selectively etching the conductive material layer in the presence of the patterned photoresist layer to form a portion of the passive element that has a top surface that is approximately coplanar with the top surface of the first conductive feature or below the top surface of the first conductive feature. 
 
     
     
       11. The method of  claim 10  wherein the first dielectric layer is comprised of a first dielectric material and the second dielectric layer is comprised of a second dielectric material having a higher thermal conductivity than the first dielectric material of the first dielectric layer. 
     
     
       12. The method of  claim 10  wherein the conductive material layer has a bottom surface in a directly contacting relationship with the second dielectric layer, or the passive element includes another conductive material layer that has a bottom surface in a directly contacting relationship with the second dielectric layer. 
     
     
       13. The method of  claim 10  wherein the first dielectric layer is comprised of a dielectric material and the first conductive feature is comprised of a conductor, and removing the first dielectric layer from the second dielectric layer comprises:
 performing a reactive ion etching process to remove the dielectric material of the first dielectric layer at a significantly higher rate than the conductor of the first conductive feature. 
 
     
     
       14. The method of  claim 10  wherein the first dielectric layer is comprised of a dielectric material and the first conductive feature is comprised of a conductor, and removing the first dielectric layer from the second dielectric layer comprises:
 exposing the first dielectric layer to a wet chemical isotropic etchant to remove the dielectric material of the first dielectric layer at a significantly higher rate than the conductor of the first conductive feature. 
 
     
     
       15. The method of  claim 10  further comprising:
 after the first dielectric layer is removed and before the conductive material layer is deposited, continuing to remove the second dielectric layer to further recess the top surface of the second dielectric layer relative to the top surface of the first conductive feature. 
 
     
     
       16. The method of  claim 10  wherein the top surface of the portion of the passive element is located below the top surface of the first conductive feature. 
     
     
       17. The method of  claim 10  wherein the passive element is a resistor, and the portion of the passive element is a body of the resistor. 
     
     
       18. The method of  claim 10  wherein the passive element is a capacitor, and the portion of the passive element is an electrode of the capacitor. 
     
     
       19. The method of  claim 10  wherein the first dielectric layer is removed from the second dielectric layer without masking a top surface of the first dielectric layer. 
     
     
       20. The method of  claim 10  further comprising:
 forming a second conductive feature extending through the layer stack, 
 wherein a recess is formed between the first and second conductive features when the first dielectric layer is removed. 
 
     
     
       21. The method of  claim 20  wherein the portion of the passive element is laterally positioned in the recess between the first and second conductive features, and further comprising:
 before the conductive material layer is etched to form the portion of the passive element, masking a corresponding portion of the conductive material layer that is laterally positioned in the recess between the first and second conductive features.