Semiconductor structure including at least one electrically conductive pillar, semiconductor structure including a contact contacting an outer layer of an electrically conductive structure and method for the formation thereof

Abstract

A semiconductor structure includes a substrate, at least one electrically conductive pillar provided over the substrate and an electrically conductive structure provided over the substrate. The electrically conductive pillar includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure also includes an inner portion and an outer layer that is provided below the inner portion and lateral to the inner portion. The electrically conductive structure annularly encloses each of the at least one electrically conductive pillar. The outer layer of each of the at least one electrically conductive pillar contacts the outer layer of the electrically conductive structure. The outer layer of the at least one electrically conductive pillar and the outer layer of the electrically conductive structure are formed of different metallic materials.

What is claimed: 
     
       1. A semiconductor structure comprising:
 a substrate; 
 a first transistor and a second transistor, said first transistor being one of a P-channel transistor and an N-channel transistor, said second transistor being the other of a P-channel transistor and an N-channel transistor; 
 at least one electrically conductive pillar positioned above said substrate and comprising a first inner portion and a first outer layer that is provided below said first inner portion and lateral to first said inner portion; and 
 a first gate electrode structure for said first transistor positioned above said substrate and comprising a second inner portion and a second outer layer that is provided below said second inner portion and lateral to said second inner portion, wherein said first gate electrode structure annularly encloses each of said at least one electrically conductive pillar, said first outer layer contacts said second outer layer and said first outer layer and said second outer layer are formed of different metallic materials. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein said second outer layer comprises a first metallic gate workfunction adjustment material adapted for adjusting a workfunction of said first gate electrode of said first transistor. 
     
     
       3. The semiconductor structure of  claim 2 , further comprising a second gate electrode for said second transistor, wherein said first outer layer comprises a second metallic gate workfunction adjustment material adapted for adjusting a workfunction of said second gate electrode of said second transistor. 
     
     
       4. The semiconductor structure of  claim 1 , further comprising:
 an interlayer dielectric positioned above said first gate electrode structure; and 
 at least one contact formed in said interlayer dielectric, each of said at least one contact providing an electrical connection to one of said at least one electrically conductive pillar. 
 
     
     
       5. The semiconductor structure of  claim 4 , wherein said at least one contact contacts said first outer layer of said electrically conductive pillar. 
     
     
       6. The semiconductor structure of  claim 1 , wherein said first transistor comprises an active region comprising a source region, a drain region and a channel region between said source region and said drain region, wherein said first gate electrode structure extends across said channel region along a channel width direction that is perpendicular to a channel length direction from said source region to said drain region, said first gate electrode structure further extends over an isolation structure adjacent said active region and said at least one electrically conductive pillar is positioned vertically above said isolation structure. 
     
     
       7. The semiconductor structure of  claim 6 , wherein said at least one electrically conductive pillar comprises two electrically conductive pillars that are each positioned vertically above said isolation structure on opposite sides of said active region. 
     
     
       8. The semiconductor structure of  claim 1 , wherein said first inner portion and said second inner portion comprise aluminum. 
     
     
       9. The semiconductor structure of  claim 1 , wherein said semiconductor structure further comprises;
 a P-channel transistor comprising a metallic P-gate workfunction adjustment material; and 
 an N-channel transistor comprising a metallic N-gate workfunction adjustment material, wherein said first outer layer of said at least one electrically conductive pillar is formed of one of said P-gate workfunction adjustment material and said N-gate workfunction adjustment material and said second outer layer of said first gate electrode structure is formed of the other of said P-gate workfunction adjustment material and said N-gate workfunction adjustment material. 
 
     
     
       10. The semiconductor structure of  claim 1 , wherein said at least one electrically conductive pillar comprises a plurality of electrically conductive pillars, wherein a spacing between adjacent ones of said plurality of electrically conductive pillars being about 2 μm or less. 
     
     
       11. The semiconductor structure of  claim 1 , wherein said first gate electrode structure has a generally rectangular shape. 
     
     
       12. The semiconductor structure of  claim 4 , wherein, for any direction perpendicular to a thickness direction of said substrate, an extension of said at least one contact in said direction is smaller than a minimum extension of said first gate electrode structure in said direction. 
     
     
       13. The semiconductor structure of  claim 12 , wherein said at least one contact is arranged such that it contacts said first and second outer layers. 
     
     
       14. A semiconductor structure comprising:
 a substrate; 
 a first transistor and a second transistor, said first transistor being one of a P-channel transistor and an N-channel transistor, said second transistor being the other of a P-channel transistor and an N-channel transistor; 
 at least one electrically conductive pillar positioned above said substrate and comprising a first inner portion and a first outer layer that is provided below said first inner portion and lateral to first said inner portion; 
 a first gate electrode structure for said first transistor positioned above said substrate and comprising a second inner portion and a second outer layer that is provided below said second inner portion and lateral to said second inner portion, wherein said first gate electrode structure annularly encloses each of said at least one electrically conductive pillar, said first outer layer contacts said second outer layer, said first outer layer and said second outer layer are formed of different metallic materials and said first and second inner portions comprise aluminum; 
 an interlayer dielectric positioned above said first gate electrode structure; and 
 at least one contact formed in said interlayer dielectric, each of said at least one contact providing an electrical connection to one of said at least one electrically conductive pillar, wherein each of said at least one contact conductively contacts said first and second outer layers. 
 
     
     
       15. The semiconductor structure of  claim 14 , wherein said second outer layer comprises a first metallic gate workfunction adjustment material adapted for adjusting a workfunction of said first gate electrode of said first transistor. 
     
     
       16. The semiconductor structure of  claim 15 , further comprising a second gate electrode for said second transistor, wherein said first outer layer comprises a second metallic gate workfunction adjustment material adapted for adjusting a workfunction of said second gate electrode of said second transistor. 
     
     
       17. The semiconductor structure of  claim 14 , wherein said first transistor comprises an active region comprising a source region, a drain region and a channel region between said source region and said drain region, wherein said first gate electrode structure extends across said channel region along a channel width direction that is perpendicular to a channel length direction from said source region to said drain region, said first gate electrode structure further extends over an isolation structure adjacent said active region and said at least one electrically conductive pillar is positioned vertically above said isolation structure. 
     
     
       18. The semiconductor structure of  claim 17 , wherein said at least one electrically conductive pillar comprises two electrically conductive pillars that are each positioned vertically above said isolation structure on opposite sides of said active region. 
     
     
       19. The semiconductor structure of  claim 14 , wherein said semiconductor structure further comprises;
 a P-channel transistor comprising a metallic P-gate workfunction adjustment material; and 
 an N-channel transistor comprising a metallic N-gate workfunction adjustment material, wherein said first outer layer of said at least one electrically conductive pillar is formed of one of said P-gate workfunction adjustment material and said N-gate workfunction adjustment material and said second outer layer of said first gate electrode structure is formed of the other of said P-gate workfunction adjustment material and said N-gate workfunction adjustment material. 
 
     
     
       20. The semiconductor structure of  claim 14 , wherein, for any direction perpendicular to a thickness direction of said substrate, an extension of said at least one contact in said direction is smaller than a minimum extension of said first gate electrode structure in said direction.