Semiconductor device with through molding vias and method of making the same

Abstract

A method of forming a semiconductor device includes bonding a capping wafer and a base wafer to form a wafer package. The base wafer includes a first chip package portion, a second chip package portion, and a third chip package portion. The capping wafer includes a plurality of isolation trenches. Each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion. The method also includes removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. The method further includes separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation.

What is claimed is: 
     
       1. A method of forming a semiconductor device, the method comprising:
 bonding a capping wafer and a base wafer to form a wafer package,
 wherein
 the base wafer comprises a first chip package portion, a second chip package portion, and a third chip package portion, and 
 the capping wafer comprises a plurality of isolation trenches, each isolation trench of the plurality of isolation trenches is substantially aligned with a corresponding trench region of one of the first chip package portion, the second chip package portion or the third chip package portion; 
 
 
 removing a portion of the capping wafer to expose a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact; and 
 separating the wafer package into a first chip package configured to perform a first operation, a second chip package configured to perform a second operation, and a third chip package configured to perform a third operation. 
 
     
     
       2. The method of  claim 1 , further comprising:
 bonding the first chip package, the second chip package, and the third chip package together with a molding compound. 
 
     
     
       3. The method of  claim 2 , further comprising:
 forming a plurality of through molding vias through the molding compound exposing the first chip package portion contact, the second chip package portion contact, and the third chip package portion contact; 
 forming a redistribution layer over the first chip package, the second chip package, and the third chip package, at least a portion of the molding compound, and in the plurality of through molding vias. 
 
     
     
       4. The method of  claim 3 , further comprising:
 forming an insulation layer over the molding compound and the redistribution layer; and 
 forming a plurality of openings in the insulation layer exposing at least a portion of the redistribution layer. 
 
     
     
       5. The method of  claim 4 , further comprising:
 forming a plurality of under bump layers in the plurality of openings; and 
 forming a plurality of solder bumps over the under bump layers. 
 
     
     
       6. The method of  claim 1 , wherein at least one of the first chip package, the second chip package or the third chip package is an accelerometer, a gyroscope, or a pressure sensor. 
     
     
       7. The method of  claim 1 , further comprising:
 placing an adhesive layer on a substrate; and 
 placing the first chip package, the second chip package and the third chip package over the adhesive layer; 
 bonding the first chip package, the second chip package and the third chip package together; and 
 removing the substrate by de-bonding the adhesive from the bonded first chip package, second chip package and third chip package. 
 
     
     
       8. A semiconductor device comprising:
 a first chip package configured to perform a first operation, the first chip package comprising a first chip package portion comprising:
 a first base wafer portion of a base wafer; and 
 a first capping wafer portion of a capping wafer, the first capping wafer portion being bonded to the first base wafer portion; 
 
 a second chip package configured to perform a second operation, the second chip package comprising a second chip package portion comprising:
 a second base wafer portion of the base wafer; and 
 a second capping wafer portion of the capping wafer, the second capping wafer portion being bonded to the second base wafer portion; 
 
 a third chip package configured to perform a third operation, the third chip package comprising a third chip package portion comprising:
 a third base wafer portion of the base wafer; and 
 a third capping wafer portion of the capping wafer, the third capping wafer portion being bonded to the third base wafer portion; and 
 
 a molding compound layer over the first chip package, the second chip package, and the third chip package, the molding compound layer having a plurality of through molding vias therein exposing a first chip package portion contact, a second chip package portion contact, and a third chip package portion contact. 
 
     
     
       9. The semiconductor device of  claim 8 , wherein at least one of the first chip package, the second chip package or the third chip package is an accelerometer, a gyroscope, or a pressure sensor. 
     
     
       10. The semiconductor device of  claim 8 , wherein at least one of the first chip package, the second chip package or the third chip package is an application specific integrated circuit (ASIC). 
     
     
       11. The semiconductor device of  claim 8 , further comprising:
 a redistribution layer over the first chip package, the second chip package, and the third chip package, and in the plurality of through molding vias; 
 an insulation layer over the molding compound; 
 a plurality of openings in the insulation layer exposing the redistribution layer; and 
 a plurality of conductive elements in the plurality of openings. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the conductive elements comprise an under bump layer and a solder bump. 
     
     
       13. The semiconductor device of  claim 11 , wherein the conductive elements comprise a conductive pillar. 
     
     
       14. The semiconductor device of  claim 11 , wherein each molding via of the plurality of through molding vias is sealed by the insulation layer. 
     
     
       15. A semiconductor device comprising:
 a first chip package configured to perform a first operation, the first chip package comprising a first chip package portion comprising:
 a first base wafer portion of a base wafer; and 
 a first capping wafer portion of a capping wafer, the first capping wafer portion being bonded to the first base wafer portion; 
 
 a second chip package configured to perform a second operation, the second chip package comprising a second chip package portion comprising:
 a second base wafer portion of the base wafer; and 
 a second capping wafer portion of the capping wafer, the second capping wafer portion being bonded to the second base wafer portion; 
 
 a third chip package configured to perform a third operation, the third chip package comprising a third chip package portion comprising:
 a third base wafer portion of the base wafer; and 
 a third capping wafer portion of the capping wafer, the third capping wafer portion being bonded to the third base wafer portion; 
 
 a CMOS chip package bonded to the first chip package, the second chip package, and the third chip package. 
 
     
     
       16. The semiconductor device of  claim 15 , wherein at least one of the first chip package, the second chip package or the third chip package is an accelerometer, a gyroscope, or a pressure sensor. 
     
     
       17. The semiconductor device of  claim 15 , further comprising:
 a redistribution layer over the first chip package, the second chip package, and the third chip package, and in electrical contact with the first chip package, the second chip package, and the third chip package; 
 an insulation layer over the redistribution layer, the insulation layer having a plurality of openings defined therein exposing the redistribution layer; and 
 a conductive element in each opening of the plurality of openings. 
 
     
     
       18. The semiconductor device of  claim 15 , wherein at least one of the first chip package, the second chip package, or the third chip package is over the CMOS chip package. 
     
     
       19. The semiconductor device of  claim 18 , further comprising:
 a redistribution layer over the first chip package, the second chip package, and the third chip package, and in electrical contact with the first chip package, the second chip package, the third chip package and the CMOS chip package. 
 
     
     
       20. The semiconductor device of  claim 15 , wherein at least two of the first chip package, the second chip package, the third chip package, and the CMOS chip package are bonded together by a molding compound.