Copper wire and dielectric with air gaps

Abstract

Approaches for fabricating copper wires in integrated circuits are provided. A method of manufacturing a semiconductor structure includes forming a wire opening in a mask. The method also includes electroplating a conductive material in the wire opening. The method additionally includes forming a cap layer on the conductive material. The method further includes removing the mask. The method still further includes forming spacers on sides of the conductive material. The method additionally includes forming a dielectric film on surfaces of the cap layer and the sidewall spacers.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor structure, comprising:
 forming a dielectric layer with a via opening; 
 forming a wire comprising:
 forming a barrier layer on and over the dielectric layer; 
 depositing an electroplated material on and over the barrier layer; 
 forming a cap layer on and over the electroplated material; and 
 depositing an insulator material on sidewalls of the electroplated material to form spacers on the sidewalls of the electroplated material; and 
 
 forming an upper dielectric layer over and around the wire and directly contacting a top surface of the cap layer, the spacers, and a top surface of the dielectric layer with the via opening, 
 wherein:
 the barrier layer comprises a first conductive material; 
 the cap layer comprises a second conductive material different than the first conductive material; 
 the spacers comprise the insulator material; and 
 the spacers are formed directly on the sidewalls of the electroplated material. 
 
 
     
     
       2. The method of  claim 1 , further comprising:
 forming a second wire; and 
 forming an air gap in the upper dielectric layer between the wire and the second wire. 
 
     
     
       3. The method of  claim 2 , wherein the second wire is on and contacting the barrier layer. 
     
     
       4. The method of  claim 3 , wherein:
 the second wire comprises a cap composed of a same material as the electroplated material; and 
 the second wire comprises sidewall spacers composed of a same material as the insulator material. 
 
     
     
       5. The method of  claim 1 , wherein:
 the first conductive material comprises Ti or TiN; 
 the second conductive material comprises Ni or CoWP; and 
 the electroplated material comprises copper. 
 
     
     
       6. The method of  claim 1 , wherein the wire has sub-micron height and width. 
     
     
       7. The method of  claim 1 , wherein the electroplated material directly contacts a via in the via opening. 
     
     
       8. The method of  claim 7 , wherein the via electrically contacts another wire. 
     
     
       9. The method of  claim 1 , further comprising:
 forming a second wire on the barrier layer, wherein: 
 the wire and the second wire have a same height; and 
 a spacing between the wire and the second wire is less than the height. 
 
     
     
       10. The method of  claim 9 , further comprising:
 forming an air gap in the upper dielectric layer between the wire and the second wire. 
 
     
     
       11. The method of  claim 1 , wherein a top surface of the spacers is at a same vertical level as a top surface of the cap layer. 
     
     
       12. The method of  claim 1 , wherein:
 the electroplated material is formed within an opening in a mask; and 
 the electroplated material is formed to a height less than the height of the mask. 
 
     
     
       13. A method of manufacturing a semiconductor structure, comprising:
 forming a wire comprising:
 forming a barrier layer; 
 depositing an electroplated material on and over the barrier layer; 
 forming a cap layer on and over the electroplated material; and 
 depositing an insulator material on sidewalls of the electroplated material to form spacers on the sidewalls of the electroplated material, 
 
 wherein:
 the barrier layer comprises a first conductive material; 
 the cap layer comprises a second conductive material different than the first conductive material; 
 the spacers comprise the insulator material; 
 an uppermost top surface of the spacers is at a same horizontal plane as an uppermost top surface of the cap layer; and 
 the spacers are formed directly on the sidewalls of the electroplated material. 
 
 
     
     
       14. The method of  claim 13 , wherein the cap layer comprises Ni(nickel) or CoWP (cobalt-tungsten-phosphide), and the method further comprises:
 forming a dielectric layer on and contacting the spacers and the cap layer. 
 
     
     
       15. The method of  claim 14 , further comprising:
 forming a lower dielectric layer with a via opening, and wherein: 
 the barrier layer is on and contacting the lower dielectric layer; 
 the barrier layer is in the via opening; 
 the dielectric layer is on and contacting a top surface of the lower dielectric layer. 
 
     
     
       16. The method of  claim 15 , further comprising:
 forming a second wire on the barrier layer wherein: the wire and the second wire have a same height, and a spacing between the wire and the second wire is less than the height; and 
 forming an air gap in the dielectric layer between the wire and the second wire. 
 
     
     
       17. A method of manufacturing a semiconductor structure, comprising:
 forming a wire comprising:
 forming a barrier layer; 
 depositing an electroplated material on and over the barrier layer; 
 forming a cap layer on and over the electroplated material; and 
 depositing an insulator material on sidewalls of the electroplated material to form spacers on the sidewalls of the electroplated material; 
 
 wherein:
 the barrier layer comprises a first conductive material; and 
 the cap layer comprises a second conductive material different than the first conductive material; 
 the spacers comprise the insulator material; 
 an uppermost top surface of the spacers is at a same horizontal plane as an uppermost top surface of the cap layer; 
 
 forming a lower dielectric layer with a via opening, wherein:
 the barrier layer is on and contacting the lower dielectric layer; 
 the barrier layer is in the via opening; 
 the dielectric layer is on and contacting a top surface of the lower dielectric layer; 
 
 forming a second wire on the barrier layer wherein:
 the wire and the second wire have a same height, and a spacing between the wire and the second wire is less than the height; and 
 
 forming an air gap in the dielectric layer between the wire and the second wire; 
 wherein:
 the electroplated material is formed within a first opening and a second opening of a mask to form the wire and the second wire, respectively; 
 the cap layer is formed on and over the electroplated material of the wire and the second wire; and 
 the cap layer on and over the electroplated material is formed to a height less than the height of the mask. 
 
 
     
     
       18. A method of manufacturing a semiconductor structure, comprising:
 forming a dielectric layer with a via opening; 
 forming a wire comprising:
 forming a barrier layer on and over the dielectric layer; 
 depositing an electroplated material on and over the barrier layer; 
 forming a cap layer on and over the electroplated material; and 
 depositing an insulator material on sidewalls of the electroplated material to form spacers on the sidewalls of the electroplated material; and 
 
 forming an upper dielectric layer over and around the wire and directly contacting a top surface of the cap layer, the spacers, and a top surface of the dielectric layer with the via opening, 
 wherein:
 the barrier layer comprises a first conductive material; 
 the cap layer comprises a second conductive material different than the first conductive material; 
 the spacers comprise the insulator material; 
 the electroplated material is formed within an opening in a mask; 
 the electroplated material is formed to a height less than the height of the mask; and 
 the cap layer is formed on and over the electroplated material and is formed to a height less than the height of the mask.