Alignment mark for semiconductor device

Abstract

Semiconductor devices and methods for manufacturing a semiconductor device include a first semiconductor substrate in which a first scribe line region and a first chip region are defined, a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate, a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined, and a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate, wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other.

What is claimed is: 
     
       1. A semiconductor device, comprising:
 a first semiconductor substrate in which a first scribe line region and a first chip region are defined; 
 a first alignment mark inside the first semiconductor substrate and in the first scribe line region so as to be spaced apart from an upper side of the first semiconductor substrate; 
 a second semiconductor substrate on the first semiconductor substrate and in which a second scribe line region and a second chip region are defined; 
 a second alignment mark inside the second semiconductor substrate and in the second scribe line region so as to be spaced apart from an upper side of the second semiconductor substrate and a lower side of the second semiconductor substrate; and 
 a through via structure inside the second chip region of the second semiconductor substrate, 
 wherein the second semiconductor substrate is on the first semiconductor substrate so that positions of the first alignment mark and the second alignment mark correspond to each other, and 
 wherein the second alignment mark overlaps laterally the through via structure in a direction that is parallel with respect to a major axis of the second semiconductor substrate. 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the first and second semiconductor substrates include silicon. 
     
     
       3. The semiconductor device of  claim 2 , wherein the first and second alignment marks are in an amorphous state. 
     
     
       4. The semiconductor device of  claim 3 , wherein the first and second alignment marks are formed by respectively irradiating the first and second semiconductor substrates with a laser. 
     
     
       5. The semiconductor device of  claim 1 , further comprising:
 a third alignment mark on a side of the first semiconductor substrate facing the second semiconductor substrate. 
 
     
     
       6. The semiconductor device of  claim 5 , wherein the third alignment mark is formed in a position that corresponds to the position of the first alignment mark. 
     
     
       7. The semiconductor device of  claim 5 , wherein an outline of the third alignment mark is positioned within and about 3.75 μum from an outline of the first alignment mark. 
     
     
       8. The semiconductor device of  claim 1 , further comprising:
 a circuit structure inside the second chip region of the second semiconductor substrate. 
 
     
     
       9. The semiconductor device of  claim 1 , wherein the first alignment mark or the second alignment mark is shaped in a form of a cross. 
     
     
       10. A semiconductor device, comprising:
 a semiconductor chip including a scribe line region; 
 a through via structure inside the semiconductor chip; and 
 a first alignment mark inside the semiconductor chip and in the scribe line region so as to be spaced apart from an upper side of the semiconductor chip and a lower side of the semiconductor chip, 
 wherein the first alignment mark overlaps laterally the through via structure in a direction that is parallel with respect to a major axis of the semiconductor chip. 
 
     
     
       11. The semiconductor device of  claim 10 , further comprising:
 a second alignment mark in a position corresponding to a position of the first alignment mark and on a lower side of the semiconductor chip, wherein the lower side and the upper side oppose each other. 
 
     
     
       12. The semiconductor device of  claim 11 , wherein the semiconductor chip includes silicon. 
     
     
       13. The semiconductor device of  claim 12 , wherein the semiconductor chip is in a crystalline state, and the first alignment mark is in an amorphous state. 
     
     
       14. The semiconductor device of  claim 11 , wherein the first alignment mark is shaped in a form of a cross. 
     
     
       15. The semiconductor device of  claim 5 , wherein an outline of the second alignment mark is positioned within about 3.75 μm from an outline of the first alignment mark. 
     
     
       16. A semiconductor device, comprising:
 a semiconductor layer including at least one scribe line region delimiting a side of at least one chip region; 
 a through via structure inside the semiconductor layer; and 
 an alignment mark within the semiconductor layer so as to be spaced apart from a first surface of the semiconductor layer on which semiconductor chips are formed and a second surface of the semiconductor layer, parallel to the first surface, 
 wherein the alignment mark and a portion of the through via structure are at a common distance from the first surface of the semiconductor layer. 
 
     
     
       17. The semiconductor device according to  claim 16 , wherein a solid state of the semiconductor layer is different than a solid state of the alignment mark. 
     
     
       18. The semiconductor device according to  claim 17 , wherein the solid state of the alignment mark is crystalline, polycrystalline or amorphous.