Method for producing a semiconductor component and a semiconductor component produced according to the method

Abstract

A method for producing a semiconductor component includes forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer. The method also includes porously etching the p-doped layer between the material of the n-doped layer to form a top electrode, and forming a cavity below the n-doped layer.

What is claimed is: 
     
       1. A method for producing a semiconductor component, comprising:
 forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer having openings; 
 porously etching the p-doped layer through the openings of the n-doped layer, the porously etched p-doped n-doped layer configured to form a top electrode of the semiconductor component, and 
 forming a cavity below the n-doped layer. 
 
     
     
       2. The method according to  claim 1 , further comprising depositing a sealing layer on the top electrode, wherein the pressure prevailing during the deposition of the sealing layer defines the pressure in the cavity. 
     
     
       3. The method according to  claim 1 , further comprising forming a bottom electrode in the component below the top electrode, wherein the bottom electrode comprises at least one of: a second sieve-like layer or a second network-like layer. 
     
     
       4. The method according to  claim 1 , further comprising forming the p-doped layer on a semiconductor substrate using an epitaxial process prior to the forming of the n-doped layer in the p-doped layer. 
     
     
       5. The method according to  claim 1 , further comprising:
 producing the cavity by producing a second porous layer under the porously-etched p-doped layer, the second porous layer having a porosity of more than approximately 70%, 
 wherein the cavity is produced from the second porous layer by an annealing step. 
 
     
     
       6. The method according to  claim 1 , wherein the semiconductor component includes at least one of: a multilayer semiconductor element, a micromechanical component or a pressure sensor. 
     
     
       7. The method according to  claim 1 , wherein the semiconductor substrate includes silicon. 
     
     
       8. The method according to  claim 5 , wherein the second porous layer has a porosity of approximately 85% to 95%. 
     
     
       9. The method according to  claim 1 , wherein the cavity forming step includes the substep of forming one of an access opening and a hollow open on one side in one of a direction of the porously-etched p-doped layer and a second porous layer. 
     
     
       10. The method according to  claim 9 , wherein the cavity forming step includes the substep of one of partially and completely removing at least one of the porously-etched p-doped layer and the second porous layer via the one of the access opening and the hollow open on one side. 
     
     
       11. The method according to  claim 1 , wherein the cavity forming step includes the substep of forming a single planar hollow under the porously-etched p-doped layer, and increasing a depth of the single planar hollow to form the cavity. 
     
     
       12. The method according to  claim 5 , wherein one of the porously-etched p-doped layer and the second porous layer is produced by at least one etching medium. 
     
     
       13. The method according to  claim 5 , wherein the semiconductor component includes a multilayer semiconductor element, and at least one of porously-etched p-doped layer and the second porous layer is produced in the respective producing step by applying an electrical field between a top and a bottom of the semiconductor element and establishing an electric current. 
     
     
       14. The method according to  claim 11 , wherein the single planar hollow forming step includes the substep of selecting process parameters so that one of pores and hollows of a second porous layer overlap one another in a lateral direction to form the single planar hollow. 
     
     
       15. The method according to  claim 1 , further comprising the step of depositing an epitaxial layer on the substrate. 
     
     
       16. The method according to  claim 15 , wherein the epitaxial layer includes a silicon layer. 
     
     
       17. The method according to  claim 15 , wherein the epitaxial layer includes a monocrystalline silicon layer. 
     
     
       18. The method according to  claim 1 , wherein the cavity is directly produced by an electrochemical etching step which includes:
 forming a single planar hollow under the porously-etched p-doped layer; and 
 increasing a depth of the single planar hollow to form the cavity. 
 
     
     
       19. The method according to  claim 18 , wherein a current density of an electrochemical etching step to produce the porously-etched p-doped layer is increased to a current density in the electrochemical etching step to produce the cavity. 
     
     
       20. The method according to  claim 1 , further comprising the step of producing an opening from the back of the substrate, wherein the opening is connected to the cavity. 
     
     
       21. A method for producing a semiconductor component, comprising:
 forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer having openings; 
 porously etching the p-doped layer through the openings of the n-doped layer, the porously etched p-doped n-doped layer configured to form a top electrode of the semiconductor component, and 
 forming a cavity below the n-doped layer by producing a second porous layer under the porously-etched p-doped layer, the second porous layer having a porosity of more than approximately 70%, 
 wherein the cavity is produced from the second porous layer by an annealing step. 
 
     
     
       22. A method for producing a semiconductor component, comprising:
 forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer having openings, 
 porously etching the p-doped layer through the openings of the n-doped layer, the porously etched p-doped n-doped layer configured to form a top electrode of the semiconductor component, and 
 forming a cavity below the n-doped layer, 
 wherein the cavity forming step includes the substep of forming a single planar hollow under the porously-etched p-doped layer, and increasing a depth of the single planar hollow to form the cavity. 
 
     
     
       23. A method for producing a semiconductor component, comprising:
 forming an n-doped layer in a p-doped layer of the semiconductor component, wherein the n-doped layer comprises at least one of: a sieve-like layer or a network-like layer having openings, 
 porously etching the p-doped layer through the openings of the n-doped layer, the porously etched p-doped n-doped layer configured to form a top electrode of the semiconductor component, and 
 forming a cavity below the n-doped layer, 
 wherein the cavity is directly produced by an electrochemical etching step which includes: 
 forming a single planar hollow under the porously-etched p-doped layer; and 
 increasing a depth of the single planar hollow to form the cavity.