Structure for a multiple-gate FET device and a method for its fabrication

Abstract

A method for forming a semiconductor device and a device made using the method are provided. In one example, the method includes forming a hard mask layer on a semiconductor substrate and patterning the hard mask layer to form multiple openings. The substrate is etched through the openings to form forming a plurality of trenches separating multiple semiconductor mesas. The trenches are partially filled with a dielectric material. The hard mask layer is removed and multiple-gate features are formed, with each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the semiconductor mesas.

What is claimed is: 
     
       1. A method for forming a semiconductor device, comprising:
 forming a hard mask layer on a semiconductor substrate;   patterning the hard mask layer to form a plurality of openings;   etching the substrate through the plurality of openings of the hard mask layer to form a plurality of trenches separating a plurality of semiconductor mesas, wherein each of the plurality of semiconductor mesas is formed to have a top portion having sidewalls of a first slope and a bottom portion having sidewalls of a second slope, and wherein each of the plurality of trenches is formed to have a top trench portion having a sidewall of the first slope and a bottom trench portion having a sidewall of the second slope, and wherein the first slope is different from the second slope;   partially filling the plurality of trenches with a dielectric material;   removing the hard mask layer; and   forming a plurality of multiple-gate features, each multiple-gate feature being in contact with a top surface and sidewalls of at least one of the plurality of semiconductor mesas.   
     
     
       2. The method of  claim 1  further comprising:
 performing a thermal oxidizing process on the plurality of semiconductor mesas to form a semiconductor oxide layer; and 
 removing the semiconductor oxide layer to narrow the plurality of semiconductor mesas before forming the plurality of multiple-gate features on the substrate. 
 
     
     
       3. The method of  claim 1  wherein the first slope ranges from about 90 degrees to about 85 degrees. 
     
     
       4. The method of  claim 1  wherein the second slope ranges from about 60 degrees to about 85 degrees. 
     
     
       5. The method of  claim 1  wherein the partially filling the plurality of trenches comprises substantially filling the plurality of bottom trench portions. 
     
     
       6. The method of  claim 1  wherein the partially filling the plurality of trenches comprises:
 substantially filling the plurality of both top and bottom trench portions to form a first group of shallow trench isolation (STI) features and a second group of STI features; 
 forming a photoresist layer patterned to cover the first group of STI features; and 
 recessing the second group of STI features such that the second group of STI features are substantially within the bottom trench portions. 
 
     
     
       7. The method of  claim 6  wherein the recessing comprises a reactive ion etching (RIE) process. 
     
     
       8. The method of  claim 1  wherein the partially filling the plurality of trenches comprises utilizing a high density plasma chemical vapor deposition (HDP-CVD) process. 
     
     
       9. The method of  claim 1  wherein the dielectric material comprises a material selected from the group consisting of silicon oxide, silicon nitride, silicon oxynitride, fluorinated silicate glass (FSG), low dielectric constant (K) materials, and combinations thereof. 
     
     
       10. The method of  claim 1  wherein the etching the substrate through the plurality of openings of the hard mask layer comprises using multiple processes. 
     
     
       11. The method of  claim 10  wherein the multiple processes comprise a method selected from the group consisting of dry etching, wet etching, and RIE. 
     
     
       12. The method of  claim 1  wherein the forming a hard mask layer comprises forming a silicon oxynitride layer. 
     
     
       13. The method of  claim 1  further comprising forming a pad layer on the substrate before forming the hard mask layer. 
     
     
       14. The method of  claim 13  wherein the pad layer comprises silicon oxide formed by a thermal oxidation process. 
     
     
       15. A method for forming a semiconductor device, comprising:
 forming a hard mask layer on a semiconductor substrate;   patterning the hard mask layer to form a plurality of openings;   etching the substrate through the plurality of openings to form a plurality of trenches separating a plurality of semiconductor mesas, wherein the plurality of semiconductor trenches are each defined by a top trench portion having a sidewall of a first slope and a bottom trench portion having a sidewall of a second slope, and each of the plurality of semiconductor mesas have a top portion having sidewalls of a first slope and a bottom portion having sidewalls of a second slope, and wherein the first slope is different from the second slope;   substantially filling the plurality of trenches to form first shallow trench isolation (STI) features in a first region and second STI features in a second region;   forming a photoresist layer patterned to cover the first STI features in the first region and leave a second STI features in the second region uncovered;   recessing the second STI features such that the second STI features are substantially within the bottom trench portions;   removing the patterned hard mask layer; and   forming a plurality of multiple-gate features on the substrate.   
     
     
       16. The method of  claim 15  wherein the recessing utilizes a reactive ion etching process. 
     
     
       17. The method of  claim 15  further comprising:
 performing a thermal oxidizing process on the plurality of top semiconductor mesas in the second region to form a semiconductor oxide layer; and 
 removing the semiconductor oxide layer. 
 
     
     
       18. A method for forming a semiconductor device, comprising:
 patterning a substrate to form a plurality of trenches;   partially filling the plurality of trenches with a dielectric material, resulting in a plurality of semiconductor mesas interposed by at least one of the plurality of trenches, wherein each of the plurality of semiconductor mesas is formed to have a top portion having sidewalls of a first slope and a bottom portion having sidewalls of a second slope, wherein each of the plurality of trenches has a top portion sidewall of a first slope and a bottom portion sidewall of a second slope, and wherein the first slope is different from the second slope; and   forming a plurality of gate electrodes on the substrate, each being in contact with a top surface and sidewalls of at least one of the plurality of semiconductor mesas.   
     
     
       19. The method of  claim 18  wherein the patterning a substrate comprises:
 forming a hard mask layer on the substrate; 
 patterning the hard mask layer to form a plurality of openings; and 
 etching the substrate through the plurality of openings of the hard mask layer to form the plurality of trenches. 
 
     
     
       20. A microelectronic product comprising:
 a substrate;   a trench formed in the substrate, the trench being partially filled with a dielectric material;   a first semiconductor portion and a second semiconductor portion, the first semiconductor portion being on an opposing sidewall of the trench from the second semiconductor portion, wherein each of the first semiconductor portion and the second semiconductor portion comprises a top semiconductor portion and a bottom semiconductor portion, the top semiconductor portion having a sidewall of a first slope and the bottom semiconductor portion having a sidewall of a second slope different from the first slope, the sidewall of the top semiconductor portion and the sidewall of the bottom semiconductor portion being sidewalls of the trench, the first semiconductor portion and the second semiconductor portion having an indent where the sidewall of the top semiconductor portion is indented from a top end of the sidewall of the bottom semiconductor portion, an upper surface of the dielectric material being level with the indent;   a gate dielectric layer extending continuously from a sidewall of the top semiconductor portion of the first semiconductor portion over and in contact with a top surface of the dielectric material in the trench and onto a sidewall of a top semiconductor portion of the second semiconductor portion, the gate dielectric being disposed over a top surface and sidewalls of the first semiconductor portion and the second semiconductor portion; and   a gate electrode over the gate dielectric.   
     
     
       21. The microelectronic product of claim 20 wherein the first slope is between about 90 degrees and about 85 degrees. 
     
     
       22. The microelectronic product of claim 20 wherein the second slope is between about 60 degrees and about 85 degrees. 
     
     
       23. The microelectronic product of claim 20 wherein the first semiconductor portion has at least two pre-selected crystal orientations, the at least two pre-selected crystal orientations being selected from the group consisting of crystal orientations (100), (110), and (111). 
     
     
       24. The microelectronic product of claim 20 wherein a bottom portion of the first semiconductor portion has a thickness ranging from 200 nm to 1,000 nm. 
     
     
       25. The microelectronic product of claim 20 wherein a top portion of the first semiconductor portion has a thickness ranging from 10 nm to 100 nm. 
     
     
       26. The microelectronic product of claim 20 wherein a width of the first semiconductor portion from one sidewall to another sidewall is between about 5 nm to about 100 nm. 
     
     
       27. The microelectronic product of claim 20 wherein the dielectric material comprises a material selected from the group consisting of fluorinated silicate glass (FSG), low dielectric constant (K) materials, and combinations thereof. 
     
     
       28. The microelectronic product of claim 20 wherein gate dielectric material comprises a high-k gate dielectric material. 
     
     
       29. The microelectronic product of claim 28 wherein the high-k gate dielectric material comprises metal oxide. 
     
     
       30. The microelectronic product of claim 28 wherein the high-k gate dielectric material comprises HfO 2 , ZrO 2 , HfSiON, HfSi x , HfSi x N y , HfAlO 2 , or NiSi x . 
     
     
       31. The microelectronic product of claim 20 further comprising another trench having a same shape as the trench, wherein the another trench is completely filled with the dielectric material. 
     
     
       32. The microelectronic product of claim 20 wherein the gate electrode comprises a metal gate electrode. 
     
     
       33. The microelectronic product of claim 32 wherein the metal gate electrode comprises titanium nitride, ruthenium, copper, or tungsten. 
     
     
       34. The microelectronic product of claim 32 wherein the metal gate electrode comprises nickel silicide. 
     
     
       35. The microelectronic product of claim 20 wherein the gate electrode is a multilayer gate electrode. 
     
     
       36. The microelectronic product of claim 20 wherein the substrate comprises a Group III-V compound semiconductor. 
     
     
       37. The microelectronic product of claim 20 wherein the first semiconductor portion comprises a first material under the gate electrode and a second material in source and drain regions. 
     
     
       38. The microelectronic product of claim 37 wherein the first material comprises germanium. 
     
     
       39. The microelectronic product of claim 38 wherein the second material comprises silicon. 
     
     
       40. The microelectronic product of claim 20 further comprising raised source/drain regions.