Source and drain dislocation fabrication in FinFETs

Abstract

A device includes a semiconductor fin over a substrate, a gate dielectric on sidewalls of the semiconductor fin, and a gate electrode over the gate dielectric. A source/drain region is on a side of the gate electrode. A dislocation plane is in the source/drain region.

What is claimed is: 
     
       1. A device comprising:
 a first semiconductor fin over a substrate; 
 a first gate dielectric on sidewalls of the first semiconductor fin; 
 a first gate electrode over the first gate dielectric; 
 a first source/drain region on a side of the first gate electrode;, the first source/drain region comprising:
 a semiconductor capping layer directly contacting the first semiconductor fin, the semiconductor capping layer comprising a first material, wherein the first material is different from a material of the substrate; 
 a first semiconductor region over the semiconductor capping layer, wherein the first semiconductor region comprises a second material different from the first material; and 
 a second semiconductor region over a top and side of the first semiconductor region, the second semiconductor region comprising a third material different from the first material, wherein the second semiconductor region has a higher concentration of dopants than the semiconductor capping layer and the first semiconductor region;  
 
 a first dislocation plane in the first source/drain region; and 
 a Shallow Trench Isolation (STI) region comprising a first portion overlapped by a portion of the first gate electrode, wherein the first dislocation plane comprises a first portion higher than a top surface of the STI region, and a second portion lower than the top surface of the STI region. 
 
     
     
       2. The device of  claim 1 , wherein the first dislocation plane has a bottom higher than a bottom surface of the STI region. 
     
     
       3. The device of  claim 1  further comprising:
 a second semiconductor fin over the substrate and parallel to the first semiconductor fin; 
 a second gate dielectric on sidewalls of the second semiconductor fin; 
 a second gate electrode over the second gate dielectric, wherein the first and the second gate electrodes are interconnected to form a continuous gate electrode; 
 a second source/drain region on a side of the second gate electrode, wherein the first and the second source/drain regions are interconnected to form a continuous source/drain region; and 
 a second dislocation plane in the second source/drain region. 
 
     
     
       4. The device of  claim 3 , wherein the STI region is free from substantial portions overlapped by the continuous source/drain region. 
     
     
       5. The device of  claim 1 , wherein outer portions of the first dislocation plane farther away from the first gate electrode are higher than inner portions of the first dislocation plane closer to the first gate electrode. 
     
     
       6. The device of  claim 1 , wherein the first source/drain region comprises a first portion comprising semiconductor region and the second semiconductor region comprise silicon and an element selected from germanium and carbon, and a second portion comprising silicon and free from the element, wherein the first dislocation plane extends into the first source/drain region. 
     
     
       7. A device comprising:
 a semiconductor fin over a substrate; 
 a gate dielectric on sidewalls of the semiconductor fin; 
 a gate electrode over the gate dielectric; 
 a Shallow Trench Isolation (STI) region comprising a portion overlapped by a portion of the gate electrode and adjoining the semiconductor fin; 
 a source region and a drain region on opposite sides of the gate electrode, wherein the STI region is located substantially between the source region and the drain region, wherein the semiconductor fin extends into the source region and the drain region, the source region and the drain region each comprising:
 a first portion of the semiconductor fin; and 
 a semiconductor capping layer on a top surface and sidewalls of the first portion of the semiconductor fin; 
 
 a first dislocation plane extending into the source region; and 
 a second dislocation plane extending into the drain region, wherein at least a first portion of each of the first dislocation plane and the second dislocation plane is over a top surface of the STI region, wherein a second portion of each of the first dislocation plane and the second dislocation plane overlap the STI region. 
 
     
     
       8. The device of  claim 7 , wherein bottoms of the first and the second dislocation planes are higher than a bottom surface of the STI region. 
     
     
       9. The device of  claim 7  further comprising:
 an additional semiconductor fin over the substrate and adjacent to the semiconductor fin, wherein the semiconductor fin and the additional semiconductor fin are on opposite sides of an entirety of the STI region, and wherein the gate electrode extends over the additional semiconductor fin. 
 
     
     
       10. The device of  claim 9 , wherein the source region and the drain region extend to opposite sides of the additional semiconductor fin. 
     
     
       11. The device of  claim 7 , wherein outer portions of the first dislocation plane farther away from the gate electrode are higher than inner portions of the first dislocation plane closer to the gate electrode. 
     
     
       12. The device of  claim 7 , wherein the source region and the drain region comprise a semiconductor material having a lattice constant different from a lattice constant of the semiconductor fin. 
     
     
       13. The device of  claim 7 , wherein the source region comprises a first portion comprising silicon and an element selected from germanium and carbon, and a second portion comprising silicon and free from the element. 
     
     
       14. A device comprising:
 a first semiconductor fin over a substrate; 
 a first gate dielectric on sidewalls of the first semiconductor fin; 
 a first gate electrode over the first gate dielectric; 
 a Shallow Trench Isolation (STI) region at least partially overlapped by the first gate electrode;  
 a first source/drain region on a side of the first gate electrode;, wherein the first semiconductor fin extends into the first source/drain region, the first source/drain region comprising:
 a first portion of the first semiconductor fin, wherein the first portion of the first semiconductor fin extends above a top surface of the STI region; and 
 a semiconductor capping layer on a top surface and sidewalls of the first portion of the first semiconductor fin, wherein the semiconductor capping layer is made of a material different from a material of the substrate; and  
 
 a first dislocation plane in the first source/drain region; and 
 a Shallow Trench Isolation (STI) region comprising a portion overlapped by a portion of the first gate electrode, wherein an entirety of the first dislocation plane is higher than a top surface of the STI region, wherein an entirety of the first dislocation plane is higher than a top surface of the STI region, wherein a portion of the first dislocation plane overlaps the STI region. 
 
     
     
       15. The device of  claim 14 , wherein the first semiconductor fin extends into the first source/drain region, wherein the first source/drain region further comprises a semiconductor capping layer on the sidewalls and a top surface of the first semiconductor fin, and wherein a portion of the first dislocation plane overlaps the STI region dislocation plane extends into the semiconductor capping layer and the first portion of the first semiconductor fin. 
     
     
       16. The device of  claim 14  further comprising:
 a second semiconductor fin over the substrate and parallel to the first semiconductor fin; 
 a second gate dielectric on sidewalls of the second semiconductor fin; 
 a second gate electrode over the second gate dielectric, wherein the first and the second gate electrodes are interconnected to form a continuous gate electrode; 
 a second source/drain region on a side of the second gate electrode, wherein the first and the second source/drain regions are interconnected to form a continuous source/drain region; and 
 a second dislocation plane in the second source/drain region. 
 
     
     
       17. The device of  claim 16 , wherein the STI region is free from substantial portions overlapped by the continuous source/drain region. 
     
     
       18. The device of  claim 14 , wherein outer portions of the first dislocation plane farther away from the first gate electrode are higher than inner portions of the first dislocation plane closer to the first gate electrode. 
     
     
       19. The device of  claim 14 , wherein the first source/drain region comprises a first portion comprising silicon and an element selected from germanium and carbon, and a second portion comprising silicon and free from the element. 
     
     
       20. A device comprising:
 a first semiconductor fin over a substrate;   a first gate dielectric on sidewalls of the first semiconductor fin;   a first gate electrode over the first gate dielectric;   a first source/drain region on a side of the first gate electrode, the first source/drain region comprising:
 a semiconductor capping layer directly contacting the first semiconductor fin, the semiconductor capping layer comprising a first material, wherein the first material is different from a material of the substrate; 
 a first semiconductor region over the semiconductor capping layer, the first semiconductor region comprising a second material different from the first material; and 
 a second semiconductor region over a top and side of the first semiconductor region, the second semiconductor region comprising a third material different from the first material, wherein the second semiconductor region has a higher concentration of dopants than the first semiconductor region and the semiconductor capping layer; 
   a first dislocation plane in the first source/drain region; and   a Shallow Trench Isolation (STI) region adjacent the first semiconductor fin, wherein the first dislocation plane comprises a first portion higher than a top surface of the STI region, and a second portion lower than the top surface of the STI region.    
     
     
       21. The device of claim 20, wherein the first dislocation plane has a bottom higher than a bottom surface of the STI region.  
     
     
       22. The device of claim 20 further comprising:
 a second semiconductor fin over the substrate and parallel to the first semiconductor fin;   a second gate dielectric on sidewalls of the second semiconductor fin;   a second gate electrode over the second gate dielectric, wherein the first and the second gate electrodes are interconnected to form a continuous gate electrode;   a second source/drain region on a side of the second gate electrode, wherein the first and the second source/drain regions are interconnected to form a continuous source/drain region; and   a second dislocation plane in the second source/drain region.    
     
     
       23. The device of claim 22, wherein the STI region is free from substantial portions overlapped by the continuous source/drain region.  
     
     
       24. A device comprising:
 a substrate having a fin structure, the fin structure having a base portion and a plurality of upper portions extending from the base portion;   a Shallow Trench Isolation (STI) region extending along sidewalls of the base portion and over the base portion between adjacent ones of the plurality of upper portions;   a gate structure extending over the plurality of upper portions; and   a first source/drain region and a second source/drain region on opposing sides of the gate structure, the first source/drain region having a first dislocation plane, the first dislocation plane extending above an upper surface of the STI region, the first source/drain region comprising:
 a first semiconductor layer made of a first material, wherein the first material is different from a material of the substrate, wherein the first semiconductor layer is in direct contact with one of the plurality of upper portions; 
 a second semiconductor layer over the first semiconductor layer, the second semiconductor layer comprising a second material different from the first material; and 
 a third semiconductor layer over a top and side of the second semiconductor layer, the third semiconductor layer comprising a third material different from the first material, wherein the third semiconductor layer has a higher concentration of dopants than the second semiconductor layer and the first semiconductor layer.  
   
     
     
       25. The device of claim 24, wherein the second source/drain region has a second dislocation plane.  
     
     
       26. The device of claim 25, wherein the second dislocation plane extends above an upper surface of the STI region.  
     
     
       27. The device of claim 25, wherein outer portions of the first dislocation plane is farther away from the gate structure are higher than inner portions of the first dislocation plane closer to the gate structure, and wherein outer portions of the second dislocation plane is farther away from the gate structure are higher than inner portions of the second dislocation plane closer to the gate structure.  
     
     
       28. The device of claim 24, further comprising a gate spacer adjacent the gate structure, wherein the first dislocation plane extends below the gate spacer.  
     
     
       29. The device of claim 28, wherein the first dislocation plane has a bottom higher than a bottom surface of the STI region.  
     
     
       30. The device of claim 24, wherein the first dislocation plane terminates between a first distance under the gate structure of 4 nm or less from an edge of the gate structure and a second distance of 12 nm or less laterally spaced apart from the edge of the gate structure.  
     
     
       31. The device of claim 24, wherein the STI region extends partially over an upper surface of the base portion of the fin structure.  
     
     
       32. The device of claim 24, wherein an entirety of the first dislocation plane is above the upper surface of the STI region.  
     
     
       33. The device of claim 24, wherein the first source/drain region and the second source/drain region comprise a different semiconductor material than the substrate.  
     
     
       34. The device of claim 33, wherein the first source/drain region extends directly over a portion of the STI region.  
     
     
       35. A device comprising:
 a substrate having a fin structure, the fin structure having a mesa and a plurality of fins extending from the mesa;   a Shallow Trench Isolation (STI) region extending along sidewalls of the mesa and over the mesa between adjacent ones of the plurality of fins;   a gate structure extending over the plurality of fins; and   a first source/drain region and a second source/drain region on opposing sides of the gate structure, the first source/drain region having a first dislocation plane, the first dislocation plane extending into an underlying semiconductor material of the substrate, the first source/drain region comprising:
 a first semiconductor layer made of a first material, wherein the first material is different from a material of the substrate, wherein the first semiconductor layer is in direct contact with one of the plurality of fins; 
 a first epitaxy region over the first semiconductor layer, the first epitaxy region comprising a second material different from the first material; and 
 a second epitaxy region, wherein the second epitaxy region is over a top and side of the first epitaxy region, wherein the second epitaxy region comprises a third material different from the first material, wherein the second epitaxy region has a higher concentration of dopants than the first semiconductor layer and the first epitaxy region.  
   
     
     
       36. The device of claim 35, wherein the plurality of fins do not extend into the first source/drain region and the second source/drain region.  
     
     
       37. The device of claim 35, wherein the first dislocation plane extends higher than an upper surface of the STI region.  
     
     
       38. The device of claim 35, wherein the first dislocation plane extends under a gate spacer adjacent the gate structure.  
     
     
       39. The device of claim 35, wherein a height of the plurality of fins in the first source/drain region and the second source/drain region is less than a height of plurality of fins under the gate structure.  
     
     
       40. The device of claim 39, wherein the STI region extends between the plurality of fins in the first source/drain region and the second source/drain region.