Inventor · disambiguated record
El Mehdi Bazizi
Also filed as: BAZIZI EL MEHDI
25 granted patents·30 pending applications·39 citations·filing 2012–2025
93Inventor score
Files withAPPLIED MATERIALS INC36GLOBALFOUNDRIES INC14GLOBALFOUNDRIES US INC2MICROMATERIALS LLC2BAZIZI EL MEHDI1
Top patents by PatentIndex Score
55 records- 0191US10121846B1Resistor structure with high resistance based on very thin semiconductor layerGLOBALFOUNDRIES INC·Filed 2017·Granted Nov 6, 2018·10 cites·19 claims
- 0286US9905707B1MOS capacitive structure of reduced capacitance variabilityGLOBALFOUNDRIES INC·Filed 2016·Granted Feb 27, 2018·6 cites·19 claims
- 0379US11437274B2Fully self-aligned viaMICROMATERIALS LLC·Filed 2020·Granted Sep 6, 2022·1 cites·9 claims
- 0479US8994107B2Semiconductor devices and methods of forming the semiconductor devices including a retrograde wellBAZIZI EL MEHDI·Filed 2012·Granted Mar 31, 2015·8 cites·11 claims
- 0578US9881841B2Methods for fabricating integrated circuits with improved implantation processesGLOBALFOUNDRIES INC·Filed 2016·Granted Jan 30, 2018·2 cites·19 claims
- 0677US2025351452A1Gate all around device with fully-depleted silicon-on-insulatorAPPLIED MATERIALS INC·Filed 2025·Application pending·0 cites
- 0775US10733354B2System and method employing three-dimensional (3D) emulation of in-kerf optical macrosGLOBALFOUNDRIES INC·Filed 2018·Granted Aug 4, 2020·2 cites·20 claims
- 0874US8853752B2Performance enhancement in transistors by providing a graded embedded strain-inducing semiconductor region with adapted angles with respect to the substrate surfaceGLOBALFOUNDRIES INC·Filed 2012·Granted Oct 7, 2014·5 cites·24 claims
- 0969US9263270B2Method of forming a semiconductor device structure employing fluorine doping and according semiconductor device structureGLOBALFOUNDRIES INC·Filed 2013·Granted Feb 16, 2016·2 cites·20 claims
- 1067US2025227915A1Methods and devices for reduced floating body effect in advanced dramAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 1166US12495582B2Self-aligned wide backside power rail contacts to multiple transistor sourcesAPPLIED MATERIALS INC·Filed 2022·Granted Dec 9, 2025·0 cites·20 claims
- 1266US9312189B2Methods for fabricating integrated circuits with improved implantation processesGLOBALFOUNDRIES INC·Filed 2014·Granted Apr 12, 2016·1 cites·15 claims
- 1366US2024234544A1Inner spacer liner for gate-all-around deviceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 1466US2025121472A1Polishing articles for hybrid bonding applicationsAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 1565US12402351B2Gate all around device with fully-depleted silicon-on-insulatorAPPLIED MATERIALS INC·Filed 2022·Granted Aug 26, 2025·0 cites·12 claims
- 1664US9711513B2Semiconductor structure including a nonvolatile memory cell and method for the formation thereofGLOBALFOUNDRIES INC·Filed 2015·Granted Jul 18, 2017·1 cites·15 claims
- 1764US2025338465A1Method and material system for backside power delivery network in static random-access memory devicesAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 1864US2024313079A1Semiconductor devices containing bi-metallic silicide with reduced contact resistivityAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 1964US2023299199A1Stress incorporation in semiconductor devicesAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 2063US2022359289A1Fully self-aligned viaMICROMATERIALS LLC·Filed 2022·Application pending·0 cites
- 2162US11929433B2Asymmetric FET for FDSOI devicesGLOBALFOUNDRIES US INC·Filed 2021·Granted Mar 12, 2024·0 cites·16 claims
- 2262US11699755B2Stress incorporation in semiconductor devicesAPPLIED MATERIALS INC·Filed 2020·Granted Jul 11, 2023·0 cites·14 claims
- 2362US10283584B2Capacitive structure in a semiconductor device having reduced capacitance variabilityGLOBALFOUNDRIES INC·Filed 2016·Granted May 7, 2019·1 cites·20 claims
- 2461US2025113577A1Semiconductor airgap spacer and fabrication methodsAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 2561US2024407170A1Structure and fabrication method of peripheral transistor with epi-si contacts in memory devicesAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 2659US2024290884A1Stress incorporation in semiconductor devicesAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 2759US2025259958A1Bonding Layers Formed of High Thermal Conductivity MaterialsAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 2859US2025311383A1Source-Drain Isolation for Complementary Field Effect TransistorsAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 2959US2024332388A1Methods of reducing backside contact resistanceAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 3059US2024290883A1Void-free stress incorporation in semiconductor devicesAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 3159US2024290885A1Enhanced mobility in semiconductor devicesAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 3258US2024234531A1Inner spacer liner for gate-all-around deviceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3357US2025212496A1Isolation formation method in high-aspect ratio cmos stacked devicesAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3457US2024332297A1Replacement source/drain contact method in complementary field effect transistor (cfet) devicesAPPLIED MATERIALS INC·Filed 2024·Application pending·0 cites
- 3557US2025212458A1Bottom-up dielectric gap-fill for device isolation during source/drain epitaxy in cfetAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3657US2024194757A1Multilayer inner spacer for gate-all-around deviceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3757US2025212459A1Metallic source/drain with stress for advanced logic transistorsAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 3856US11705490B2Graded doping in power devicesAPPLIED MATERIALS INC·Filed 2021·Granted Jul 18, 2023·0 cites·19 claims
- 3956US2025140604A1Via shaping between metal layers for controlled resistanceAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 4055US2024014214A1INTEGRATING STRAIN SiGe CHANNEL PMOS FOR GAA CMOS TECHNOLOGYAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 4154US11899376B1Methods for forming alignment marksAPPLIED MATERIALS INC·Filed 2022·Granted Feb 13, 2024·0 cites·20 claims
- 4254US11245032B2Asymmetric FET for FDSOI devicesGLOBALFOUNDRIES US INC·Filed 2019·Granted Feb 8, 2022·0 cites·12 claims
- 4354US2025331284A1Sequential self-aligning method in complementary field effect transistor devicesAPPLIED MATERIALS INC·Filed 2025·Application pending·0 cites
- 4454US2023170400A1Gate all around transistor architecture with fill-in dielectric materialAPPLIED MATERIALS INC·Filed 2022·Application pending·0 cites
- 4554US2023260909A1Gate all around backside power rail with diffusion breakAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 4653US12074196B2Gradient doping epitaxy in superjunction to improve breakdown voltageAPPLIED MATERIALS INC·Filed 2021·Granted Aug 27, 2024·0 cites·12 claims
- 4751US2024258375A1Silicon carbide transistor with channel counter-doping and pocket-dopingAPPLIED MATERIALS INC·Filed 2023·Application pending·0 cites
- 4850US10680065B2Field-effect transistors with a grown silicon-germanium channelGLOBALFOUNDRIES INC·Filed 2018·Granted Jun 9, 2020·0 cites·8 claims
- 4950US2023067331A1Source drain formation in gate all around transistorAPPLIED MATERIALS INC·Filed 2022·Application pending·0 cites
- 5049US2025218870A1Self-aligning backside gate connectionAPPLIED MATERIALS INC·Filed 2025·Application pending·0 cites
Showing the top 50 of 55 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →