Enhanced mobility in semiconductor devices

Abstract

The present technology includes semiconductor devices with improved stress in a channel region. The semiconductor device includes a substrate, a source region, a drain region, a channel region that includes at least one channel located between the source and the drain. Devices include a first gate region having a first self-aligned single diffusion break in a n-MOS region, and a second gate region includes having a self-aligned single diffusion break in a p-MOS region. The second self-aligned single diffusion break also contains a liner and a compressive stressed material, where the stressed metal fill exhibits a compressive stress of about 350 MPa or greater.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate;   a source region;   a drain region;   a channel region comprising at least one channel located between the source and the drain;   a first gate region comprising a first self-aligned single diffusion break in a n-MOS region, wherein the first self-aligned single diffusion break comprises a first liner and a first fill material; and   a second gate region comprising a second self-aligned single diffusion break in a p-MOS region, wherein the second self-aligned single diffusion break comprises a compressive stressed fill material, and wherein compressive stressed fill material is characterized by a compressive stress of greater than or about 350 MPa.   
     
     
         2 . The semiconductor device of  claim 1 , where the first fill material is a neutral stressed material or a tensile stressed material. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the first fill material, the compressive stressed fill material, or both the first fill material and the compressive stressed fill material comprises a dielectric fill material. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the first fill material and the compressive stressed fill material both comprise dielectric fill materials, wherein the first fill material is different from the compressive stressed fill material. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the dielectric fill material comprises silicon nitride, a silicon oxynitride, silicon dioxide, or a combination thereof. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the second self-aligned single diffusion break comprises a second liner. 
     
     
         7 . The semiconductor device of  claim 6 , wherein the first liner, the second liner, or both the first liner and the second liner comprise a dielectric liner material. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the dielectric liner material comprises silicon nitride, a silicon oxynitride, silicon dioxide, or a combination thereof. 
     
     
         9 . The semiconductor device of  claim 7 , wherein the dielectric liner material of the first liner has an etch rate that is different than an etch rate of the first fill material. 
     
     
         10 . The semiconductor device of  claim 7 , wherein the dielectric liner material of the second liner is selected from a same material or a different material from the compressive stressed fill material. 
     
     
         11 . The semiconductor device of  claim 7 , wherein the second liner comprises silicon nitride, silicon dioxide, or a combination thereof, and the compressive stressed fill material comprises silicon dioxide, silicon nitride, or a combination thereof. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the first fill material comprises silicon nitride, silicon dioxide, or a combination thereof, wherein the compressive stressed fill material is different than the first fill material. 
     
     
         13 . The semiconductor device of  claim 1 , wherein the semiconductor device is a nanosheet field-effect transistor or a complementary field-effect transistor and/or wherein the semiconductor device is a gate-all-around complementary metal-oxide-semiconductor. 
     
     
         14 . A semiconductor processing system, comprising:
 a first processing chamber;   a second processing chamber;   a third processing chamber; and   a system controller configured to
 pattern a substrate in the first processing chamber, 
 etch a first shallow trench isolation in a first gate region and a second shallow trench isolation in a second gate region of a semiconductor device, wherein the first gate region is a n-MOS region and the second gate region is a p-MOS region, in the second processing chamber, 
 line the first shallow trench isolation and the second shallow trench isolation with a dielectric liner, fill the first shallow trench isolation and second shallow trench isolation with a neutral stressed material or a tensile stressed material, remove the neutral stressed material or tensile stressed material from the first shallow trench isolation, and fill the first shallow trench isolation with a compressive stressed material, in the third processing chamber. 
   
     
     
         15 . A method of forming a semiconductor device, comprising:
 etching a first shallow trench isolation in a first gate region and a second shallow trench isolation in a second gate region of the semiconductor device, wherein the first gate region is a n-MOS region and the second gate region is a p-MOS region, wherein the semiconductor device contains a substrate, a source region, a drain region, a channel region containing at least one channel located between the source and the drain;   lining the first shallow trench isolation and the second shallow trench isolation with a liner;   filling the lined first shallow trench isolation and second shallow trench isolation with a neutral stressed or tensile stressed material;   etching the neutral stressed material or tensile stressed material from the second shallow trench isolation; and   filling the etched second shallow trench isolation with a compressive stressed material.   
     
     
         16 . The method of  claim 15 , wherein no polishing step is conducted between filling the lined first shallow trench isolation with the neutral stressed or tensile stressed material and filling the etched second shallow trench isolation with the compressive stressed material. 
     
     
         17 . The method of  claim 15 , wherein etching the neutral stressed material or tensile stressed material is a wet etching or a dry etching process. 
     
     
         18 . The method of  claim 17 , wherein the liner comprises a dielectric liner material having an etch rate that is different than an etch rate of the neutral stressed material or tensile stressed material. 
     
     
         19 . The method of  claim 18 , wherein the liner comprises silicon nitride, a silicon oxynitride, silicon dioxide, or a combination thereof. 
     
     
         20 . The method of  claim 19 , wherein the compressive stressed material comprises silicon nitride, and wherein the neutral stressed or tensile stressed material comprises silicon nitride or silicon dioxide.