Fully self-aligned via

Abstract

Apparatuses and methods to provide a fully self-aligned via are described. A first metallization layer comprises a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer. A capping layer is on the first insulating layer, and a second insulating layer is on the capping layer. A second metallization layer comprises a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer. The set of second conductive lines extend along a second direction that crosses the first direction at an angle. At least one via is between the first metallization layer and the second metallization layer. The via is self-aligned along the second direction to one of the first conductive lines. The tapering angle of the via opening may be in a range of from about 60° to about 120°.

What is claimed is: 
     
         1 . An electronic device comprising:
 a first metallization layer comprising a set of first conductive lines extending along a first direction on a first insulating layer on a substrate, the set of first conductive lines recessed below a top portion of the first insulating layer;   a capping layer on the first insulating layer;   a second insulating layer on the capping layer;   a second metallization layer comprising a set of second conductive lines on the second insulating layer and on a third insulating layer above the first metallization layer, the set of second conductive lines extending along a second direction that crosses the first direction at an angle; and   at least one via between the first metallization layer and the second metallization layer, the at least one via having a trench portion that is a part of one of the second conductive lines and a via portion underneath the trench portion, the trench portion having a width along the second direction greater than the width along the second direction of the via portion, wherein the at least one via is self-aligned along the second direction to one of the first conductive lines and the at least one via is self-aligned along the first direction to one of the second conductive lines, the second direction crossing the first direction at an angle, wherein the at least one via has a tapering angle in a range of from about 60° to about 120°.   
     
     
         2 . The electronic device of  claim 1 , wherein the third insulating layer is etch selective relative to the second insulating layer. 
     
     
         3 . The electronic device of  claim 1 , wherein the first metallization layer and the second metallization layer independently comprise one or more of copper (Cu), ruthenium (Ru), nickel (Ni), cobalt (Co), chromium (Cr), iron (Fe), manganese (Mn), titanium (Ti), aluminum (Al), hafnium (Hf), tantalum (Ta), tungsten (W), vanadium (V), molybdenum (Mo), palladium (Pd), gold (Au), silver (Ag), platinum (Pt), indium (In), tin (Sn), lead (Pb), antimony (Sb), bismuth (Bi), zinc (Zn), or cadmium (Cd). 
     
     
         4 . The electronic device of  claim 1 , wherein the first insulating layer, the second insulating layer, and the third insulating layer, are independently selected from: oxides, carbon doped oxides, porous silicon dioxide, carbides, oxycarbides, nitrides, oxynitrides, oxycarbonitrides, polymers, phosphosilicate glass, fluorosilicate (SiOF) glass, organosilicate glass (SiOCH), or any combinations thereof. 
     
     
         5 . The electronic device of  claim 1 , wherein the capping layer comprises silicon nitride (SiN). 
     
     
         6 . The electronic device of  claim 1 , further comprising one or more of a conformal first liner between the first conductive lines and the first insulating layer, a conformal second liner on the capping layer and the first conductive lines, and a conformal third liner on the conformal second liner, wherein the conformal first liner, the conformal second liner, and the conformal third liner independently comprise one or more of titanium nitride (TiN), titanium (Ti), tantalum (Ta), or tantalum nitride (TaN), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), silicon nitride (SiN), or silicon carbonitride (SiCN). 
     
     
         7 . A processor-implemented method for forming fully self-aligned vias, the method comprising:
 receiving data for a first configuration to control depositing first conductive lines in at least one trench formed in a capping layer and a first insulating layer on a substrate, the first conductive lines extending along a first direction on the first insulating layer;   receiving data for a second configuration to control recessing the first conductive lines, a top surface of the recessed first conductive lines recessed below a top surface of a capping layer on the first insulating layer;   receiving data for a third configuration to control selectively growing a seed layer on the recessed first conductive lines and forming pillars on the seed layer on the recessed first conductive lines;   receiving data for a fourth configuration to control depositing a second insulating layer between the pillars;   receiving data for a fifth configuration to control removing the pillars to form trenches in the second insulating layer;   receiving data for a sixth configuration to control depositing a third insulating layer through the trenches onto the recessed first conductive lines;   receiving data for a seventh configuration to control etching the third insulating layer selectively relative to the second insulating layer to form a fully self-aligned via opening down to one of the recessed first conductive lines, wherein a tapering angle of the fully self-aligned via opening is in a range of from about 60° to about 120°;   receiving data for an eighth configuration to control selectively growing a seed layer on the recessed first conductive lines, wherein the pillars are formed on the seed layer;   receiving data for a ninth configuration to control forming a hard mask layer on at least one of the second insulating layer and the third insulating layer;   receiving data for a tenth configuration to control depositing a conformal first liner on the recessed first conductive lines;   receiving data for an eleventh configuration to control depositing a conductive layer into the fully self-aligned via opening;   receiving data for a twelfth configuration to control depositing one or more of a conformal first liner between the first conductive lines and the first insulating layer, a conformal second liner on the capping layer and the first conductive lines, and a third conformal liner on the second conformal liner; and   performing one or more of the first configuration, second configuration, third configuration, fourth configuration, fifth configuration, sixth configuration, seventh configuration, eighth configuration, ninth configuration, tenth configuration, eleventh configuration, or twelfth configuration.