Group IIIA-N HEMT with a tunnel diode in the gate stack

Abstract

One example provides an enhancement-mode High Electron Mobility Transistor (HEMT) includes a substrate, a Group IIIA-N active layer over the substrate, a Group IIIA-N barrier layer over the active layer, and at least one isolation region through the barrier layer to provide an isolated active area having the barrier layer on the active layer. A gate stack is located between source and drain contacts to the active layer. A tunnel diode in the gate stack includes an n-GaN layer on an InGaN layer on a p-GaN layer located on the barrier layer.

The invention claimed is: 
     
       1. An electronic device, comprising:
 a substrate; 
 a Group IIIA-N active layer on said substrate; 
 a Group IIIA-N barrier layer on said active layer; 
 at least one isolation region through said barrier layer to provide at least one isolated active area comprising said barrier layer on said active layer; 
 a p-GaN layer on said barrier layer; 
 a tunnel diode comprising a n-GaN layer on an InGaN layer on said p-GaN layer; 
 a gate over said n-GaN layer; 
 a drain having a drain contact on said barrier layer to provide contact to said active layer, and 
 a source having a source contact on said barrier layer to provide contact to said active layer. 
 
     
     
       2. The electronic device of  claim 1 , wherein said InGaN layer is doped n-type. 
     
     
       3. The electronic device of  claim 1 , wherein said InGaN layer is doped p-type. 
     
     
       4. The electronic device of  claim 1 , wherein said InGaN layer includes a linearly graded In concentration in a thickness direction for reducing a barrier voltage of said tunnel diode. 
     
     
       5. The electronic device of  claim 1 , wherein a thickness of said InGaN layer is from 3.5 nm to 100 nm. 
     
     
       6. The electronic device of  claim 1 , wherein said substrate comprises sapphire, silicon, or silicon carbide (SiC). 
     
     
       7. The electronic device of  claim 1 , wherein said gate comprises titanium or aluminum. 
     
     
       8. The electronic device of  claim 1 , wherein said E-mode HEMT is part of an integrated circuit (IC) formed in and on said substrate. 
     
     
       9. The electronic device of  claim 1 , wherein said E-mode HEMT is a first E-mode HEMT and further comprising at least a second E-mode HEMT, wherein said InGaN layer for said first E-mode HEMT and said second E-mode HEMT have a different thickness for providing a different threshold voltage (V T ) for said first E-mode HEMT compared to said second E-mode HEMT. 
     
     
       10. The electronic device of  claim 9 , further comprising a depletion-mode HEMT on said IC. 
     
     
       11. The electronic device of  claim 1 , wherein said p-GaN layer includes both magnesium and silicon doping. 
     
     
       12. An integrated circuit, comprising:
 a gate stack located over a first group IIIA-N layer, the first group IIIA-N layer being located on a second group IIIA-N layer, and the gate stack having a topmost n-type group IIIA-N layer; and 
 a gate electrode directly on the topmost n-type group IIIA-N layer. 
 
     
     
       13. The integrated circuit of  claim 12 , wherein said n-type layer comprises silicon. 
     
     
       14. The integrated circuit of  claim 12 , wherein said gate stack comprises an InGaN layer between two GaN layers. 
     
     
       15. The integrated circuit of  claim 12 , wherein said gate electrode comprises Ti or Al. 
     
     
       16. The integrated circuit of  claim 12 , wherein said gate stack is a first gate stack of a first transistor, and further comprising forming a second gate stack of a second transistor on the first group IIIA-N layer, the first gate stack including a first ternary semiconductor layer between two binary semiconductor layers, and the first gate stack including a second ternary semiconductor layer between two binary semiconductor layers, wherein the first and second ternary semiconductor layers have different thicknesses. 
     
     
       17. The integrated circuit of  claim 12 , further comprising source and drain electrodes located over the first group IIIA-N layer and formed from a same metal layer as the gate electrode. 
     
     
       18. A transistor, comprising:
 source and drain electrodes located over a group IIIA-N barrier layer; and 
 a gate stack comprising a tunnel diode located on said barrier layer between the source electrode and the drain electrode. 
 
     
     
       19. The transistor of  claim 18 , wherein said gate stack includes a topmost group IIIA-N layer doped with silicon. 
     
     
       20. The transistor of  claim 18 , wherein said gate stack comprises an InGaN layer between an n-type GaN layer and a p-type GaN layer, said gate electrode being formed directly on said n-type GaN layer. 
     
     
       21. The transistor of  claim 18 , wherein said gate electrode comprises Ti or Al.