Semiconductor device with fin end spacer dummy gate and method of manufacturing the same

Abstract

A semiconductor device includes a plurality of fins on a substrate. A fin liner is formed on an end surface of each of the plurality of fins. An insulating layer is formed on the plurality of fins. A plurality of polycrystalline silicon layers are formed on the insulating layer. A source/drain epitaxial layer is formed in a source/drain space in each of the plurality of fins. One of the polycrystalline silicon layers is formed on a region spaced-apart from the fins.

What is claimed is: 
     
       1. A method of manufacturing a semiconductor device, comprising:
 forming a first isolation insulating layer between fins; 
 forming a sacrificial oxide layer over the fins and the first isolation insulating layer; 
 forming first sacrificial gate layers on the fins and second sacrificial gate layers on edge regions of the fins at an end in a lengthwise direction of the fins; 
 forming sidewall spacer layers on opposing side faces of the first and second sacrificial gate layers; 
 etching source/drain regions of the fins, which are not covered by the sidewall spacer layers and the first and second sacrificial gate layers, thereby forming source/drain spaces; 
 forming source/drain epitaxial layers in the source/drain spaces; 
 forming interlayer dielectric layers on the source/drain epitaxial layers; 
 at least partially removing the second sacrificial gate layers, thereby forming second gate spaces; and 
 forming spacer dummy gate layers in the second gate spaces,
 wherein the second sacrificial gate layers are only partially removed leaving remaining second sacrificial layers and the spacer dummy gate layers are formed on the remaining second sacrificial layers. 
 
 
     
     
       2. The method of  claim 1 , wherein a thickness of the spacer dummy gate layers is smaller than a thickness of the remaining second sacrificial gate layers. 
     
     
       3. The method of  claim 1 , wherein the first and second sacrificial gate layers are made of polycrystalline silicon. 
     
     
       4. A method of manufacturing a semiconductor device, comprising:
 forming a fin protruding an isolation insulating layer, wherein a liner layer is disposed on a bottom of the fin; 
 forming a sacrificial gate dielectric layer over the fin and the isolation insulating layer; 
 forming a first sacrificial gate layer over an edge of the fin; 
 forming sidewall spacer layers on opposing side face of the first sacrificial gate layer; 
 etching a region of the fin adjacent to the first sacrificial gate layer, which is not covered by the sidewall spacer layers and the first sacrificial gate layer, thereby forming a source/drain space; 
 forming a source/drain epitaxial layer in the source/drain space; 
 forming an interlayer dielectric layer over the source/drain epitaxial layers; 
 at least partially removing the first sacrificial gate layer, thereby forming a first gate spaces; and 
 forming a spacer dummy gate layer in the first gate spaces,
 wherein the first sacrificial gate layer is only partially removed leaving a remaining first sacrificial layer, and the spacer dummy gate layer is formed on the remaining first sacrificial layers. 
 
 
     
     
       5. The method of  claim 4 , wherein a top of the liner layer is below a top of the isolation insulating layer. 
     
     
       6. The method of  claim 4 , wherein a top of the liner layer is above a top of the isolation insulating layer. 
     
     
       7. The method of  claim 4 , wherein a thickness of the spacer dummy gate layer is smaller than a thickness of the remaining first sacrificial gate layer. 
     
     
       8. The method of  claim 4 , wherein a bottom of the remaining first sacrificial layer has a step having an upper portion located above the fin and a lower portion located above the isolation insulating layer. 
     
     
       9. The method of  claim 4 , wherein the sacrificial gate dielectric layer under the bottom of the remaining first sacrificial layer is in contact with the fin, the liner and the isolation insulating layer. 
     
     
       10. The method of  claim 1 , wherein the sacrificial gate dielectric layer under the bottom of the spacer dummy gate layer is in contact with the fin, the liner and the isolation insulating layer. 
     
     
       11. The method of  claim 1 , wherein at the first and second sacrificial gate layers are made of polycrystalline silicon. 
     
     
       12. A method of manufacturing a semiconductor device, comprising:
 forming first fin and second fin, the first and second fins being aligned along a lengthwise direction of the first and second fins, wherein a liner layer is disposed on side faces of the first and second fins; 
 forming a dummy oxide layer on an isolation insulating layer and the first and second fins; 
 forming a first dummy gate layer over the first fin and a second dummy gate layer; 
 forming sidewall spacer layers on the first and second dummy gate layers; 
 etching source/drain regions of the first fin, which are not covered by the sidewall spacer layers, thereby forming source/drain spaces; 
 forming source/drain epitaxial layers in the source/drain spaces; 
 forming an interlayer dielectric layer over the source/drain epitaxial layers and the first and second dummy gate layers; and 
 forming a spacer dummy gate layer over a recessed second dummy gate layer, 
 wherein one layer of the source/drain epitaxial layers is adjacent to the first dummy gate layer and the spacer dummy gate layer, wherein one of the sidewall spacers is disposed between the one layer of the source/drain epitaxial layers and the first dummy gate layer and another sidewall spacer of the sidewall spaces is disposed between the one layer of the source/drain epitaxial layers and the spacer dummy gate layer. 
 
     
     
       13. The method of  claim 12 , wherein the spacer dummy gate is disposed over an edge of the first fin. 
     
     
       14. The method of  claim 13 , wherein the dummy oxide layer covers the edge of the first fin under the spacer dummy gate layer. 
     
     
       15. The method of  claim 12 , wherein the spacer dummy gate is disposed over a region between the first and second fins.