Method of forming MOSFET structure

Abstract

Devices are described herein that include an epitaxial layer, a cap layer above the epitaxial layer, a gate layer adjacent to the epitaxial layer on which an etching process is performed, a trench above the cap layer, and a source/drain portion includes the epitaxial layer.

What is claimed is: 
     
       1. A semiconductor structure comprising:
 an epitaxial layer; 
 a cap layer above the epitaxial layer, wherein an entirety of the cap layer is directly on the epitaxial layer; 
 a gate layer adjacent to the epitaxial layer; 
 a trench above the cap layer; 
 a convex-topped protection layer within the trench and above the cap layer; and 
 a source/drain portion includes the epitaxial layer. 
 
     
     
       2. The semiconductor structure of  claim 1 , wherein the source/drain portion further includes the cap layer above the epitaxial layer. 
     
     
       3. The semiconductor structure of  claim 1 , wherein the gate layer comprises:
 a first gate having a first metal portion, a first gate ceiling, a first gate bottom, a first left-side spacer, and a first right-side spacer; 
 a second gate having a second metal portion, a second gate ceiling, a second gate bottom, a second left-side spacer, and a second right-side spacer; and 
 a third gate having a third metal portion, a third gate ceiling, a third gate bottom, a third left-side spacer, and a third right-side spacer. 
 
     
     
       4. The semiconductor structure of  claim 3 , wherein the first gate ceiling and the second gate ceiling are partially recessed relative to a cap of the source/drain. 
     
     
       5. The semiconductor structure of  claim 1 , wherein the cap layer comprises silicon-germanium. 
     
     
       6. The semiconductor structure of  claim 1 , wherein the epitaxial layer is partially embedded within a substrate. 
     
     
       7. A semiconductor structure comprising:
 a source/drain portion having an epitaxial layer and a cap layer above the epitaxial layer, wherein an entirety of the cap layer substantially overlaps an entirety of the epitaxial layer with respect to a cross-sectional view; 
 a gate layer adjacent to the epitaxial layer and the cap layer; and 
 a dielectric layer above the cap layer; 
 a trench above the cap layer, wherein sidewalls of the trench comprise the gate layer and the dielectric layer above the gate layer; 
 a convex-topped protection layer within the trench and above the cap layer; 
 wherein the gate layer is etched without damaging the epitaxial layer of the source/drain portion. 
 
     
     
       8. A semiconductor structure comprising:
 an epitaxial layer; 
 a cap layer above the epitaxial layer, wherein an entirety of the cap layer is directly on the epitaxial layer; 
 a gate layer adjacent to the epitaxial layer and the cap layer; 
 a convex-topped protection layer within a trench and above the cap layer; and 
 a dielectric layer above the cap layer and the gate layer. 
 
     
     
       9. The semiconductor structure of  claim 8 , wherein the epitaxial layer and the cap layer constitute a source/drain portion of the semiconductor structure. 
     
     
       10. The semiconductor structure of  claim 8 , wherein the trench extends through the dielectric layer. 
     
     
       11. The semiconductor structure of  claim 8 , wherein the trench extends through the dielectric layer. 
     
     
       12. The semiconductor structure of  claim 8 , wherein a topmost surface of the epitaxial layer is substantially coplanar with a bottommost surface of the cap layer. 
     
     
       13. The semiconductor structure of  claim 8 , wherein the gate layer of the semiconductor structure is etched. 
     
     
       14. The semiconductor structure of  claim 8 , wherein the gate layer comprises:
 a first gate having a first metal portion, a first gate ceiling, a first gate bottom, a first left-side spacer, and a first right-side spacer; 
 a second gate having a second metal portion, a second gate ceiling, a second gate bottom, a second left-side spacer, and a second right-side spacer; and 
 a third gate having a third metal portion, a third gate ceiling, a third gate bottom, a third left-side spacer, and a third right-side spacer. 
 
     
     
       15. The semiconductor structure of  claim 7 , wherein the protection layer includes silicon. 
     
     
       16. The semiconductor structure of  claim 15 , wherein the dielectric layer is positioned above the source/drain portion and the gate layer. 
     
     
       17. The semiconductor structure of  claim 15 , wherein the protection layer includes germanium. 
     
     
       18. The semiconductor structure of  claim 15 , wherein the gate layer comprises:
 a first gate having a first metal portion, a first gate ceiling, a first gate bottom, a first left-side spacer, and a first right-side spacer; 
 a second gate having a second metal portion, a second gate ceiling, a second gate bottom, a second left-side spacer, and a second right-side spacer; and 
 a third gate having a third metal portion, a third gate ceiling, a third gate bottom, a third left-side spacer, and a third right-side spacer. 
 
     
     
       19. The semiconductor structure of  claim 18 , wherein the first gate ceiling, the second gate ceiling, and the third gate ceiling comprise silicon nitride. 
     
     
       20. The semiconductor structure of  claim 15 , wherein the cap layer comprises germanium.