Semiconductor package and method of manufacturing semiconductor package

Abstract

A semiconductor package includes an encapsulated semiconductor device and a redistribution structure. The encapsulated semiconductor device includes a semiconductor device encapsulated by an encapsulating material. The redistribution structure overlays the encapsulated semiconductor device and includes a plurality of vias and a redistribution line. The plurality of vias are located on different layers of the redistribution structure respectively and connected to one another through a plurality of conductive lines, wherein, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines. The redistribution line is disposed under the plurality of conductive lines and connects corresponding one of the plurality of vias and electrically connected to the semiconductor device through the plurality of vias.

What is claimed is: 
     
       1. A semiconductor package, comprising:
 an encapsulated semiconductor device comprising a semiconductor device encapsulated by an encapsulating material; and 
 a redistribution structure overlying the encapsulated semiconductor device and comprising:
 a plurality of vias located on different layers of the redistribution structure respectively and connected to one another through a plurality of conductive lines, wherein, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines; and 
 a redistribution line disposed under the plurality of conductive lines and connecting corresponding one of the plurality of vias and electrically connected to the semiconductor device through the plurality of vias. 
 
 
     
     
       2. The semiconductor package as claimed in  claim 1 , further comprising a plurality of conductive bumps bonded between the semiconductor device and the redistribution structure, and one of the plurality of conductive bumps is bonded to an uppermost one of the plurality of vias. 
     
     
       3. The semiconductor package as claimed in  claim 2 , wherein the one of the plurality of conductive bumps is closest to an edge of the semiconductor device. 
     
     
       4. The semiconductor package as claimed in  claim 1 , further comprising a substrate and a plurality connectors, wherein the redistribution structure is bonded to the substrate through the plurality of connectors. 
     
     
       5. The semiconductor package as claimed in  claim 1 , wherein the angle ranges substantially from 20° to 90°. 
     
     
       6. The semiconductor package as claimed in  claim 1 , wherein the plurality of vias do not overlap with one another from a top view. 
     
     
       7. The semiconductor package as claimed in  claim 1 , wherein a shortest horizontal distance between one of the plurality of vias bonded to the semiconductor device and a closest edge of the semiconductor device is shorter than a shortest horizontal distance between one of the plurality of vias connecting the redistribution line and the closest edge of the semiconductor device. 
     
     
       8. The semiconductor package as claimed in  claim 1 , wherein, from a top view, an included angle greater than zero is included between one of the plurality of conductive lines and the redistribution line. 
     
     
       9. A semiconductor package, comprising:
 a semiconductor device; and 
 a redistribution structure overlying the semiconductor device and comprising:
 a plurality of vias located on different layers of the redistribution structure respectively and connected to one another through a plurality of conductive lines; and 
 a redistribution line disposed under the plurality of conductive lines and connecting corresponding one of the plurality of vias, wherein, from a top view, an included angle greater than zero is included between one of the plurality of conductive lines and the redistribution line. 
 
 
     
     
       10. The semiconductor package as claimed in  claim 9 , further comprising a plurality of conductive bumps bonded between the semiconductor device and the redistribution structure, and one of the plurality of conductive bumps is bonded to an uppermost one of the plurality of vias. 
     
     
       11. The semiconductor package as claimed in  claim 9 , further comprising a substrate and a plurality connectors, wherein the redistribution structure is bonded to the substrate through the plurality of connectors. 
     
     
       12. The semiconductor package as claimed in  claim 9 , wherein
 an angle greater than zero is included between adjacent two of the plurality of conductive lines. 
 
     
     
       13. The semiconductor package as claimed in  claim 12 , wherein the angle ranges substantially from 20° to 90°. 
     
     
       14. The semiconductor package as claimed in  claim 9 , wherein the plurality of vias do not overlap with one another from a top view. 
     
     
       15. The semiconductor package as claimed in  claim 9 , further comprising an encapsulating material disposed over the redistribution structure and encapsulating the semiconductor device. 
     
     
       16. The semiconductor package as claimed in  claim 9 , wherein a horizontal distance between an uppermost one of the plurality of vias, which is vertically closest to the semiconductor device, and a closest edge of the semiconductor device is shorter than a horizontal distance between a bottommost one of the plurality of vias, which is vertically closest to the redistribution line, and the closest edge of the semiconductor device. 
     
     
       17. A semiconductor package, comprising:
 a semiconductor device; and 
 a redistribution structure over the semiconductor device and comprising:
 a plurality of vias located on different layers of the redistribution structure respectively and connected to one another through a plurality of conductive lines, wherein, from a top view, an angle greater than zero is included between adjacent two of the plurality of conductive lines; and 
 
 a redistribution line disposed under the plurality of conductive lines electrically connected to the semiconductor device through the plurality of vias. 
 
     
     
       18. The semiconductor package as claimed in  claim 17 , wherein an angle greater than zero is included between adjacent two of the plurality of conductive lines. 
     
     
       19. The semiconductor package as claimed in  claim 18 , wherein the angle ranges substantially from 20° to 90°. 
     
     
       20. The semiconductor package as claimed in  claim 17 , wherein a horizontal distance between an uppermost one of the plurality of vias, which is vertically closest to the semiconductor device, and a closest edge of the semiconductor device is shorter than a horizontal distance between a bottommost one of the plurality of vias, which is vertically closest to the redistribution line, and the closest edge of the semiconductor device.