Integrated circuits with gate cut features

Abstract

Examples of an integrated circuit with gate cut features and a method for forming the integrated circuit are provided herein. In some examples, a workpiece is received that includes a substrate and a plurality of fins extending from the substrate. A first layer is formed on a side surface of each of the plurality of fins such that a trench bounded by the first layer extends between the plurality of fins. A cut feature is formed in the trench. A first gate structure is formed on a first fin of the plurality of fins, and a second gate structure is formed on a second fin of the plurality of fins such that the cut feature is disposed between the first gate structure and the second gate structure.

What is claimed is: 
     
       1. A device comprising:
 a substrate; 
 a first fin and a second fin extending from the substrate; 
 a dielectric layer extending between the first fin and the second fin; 
 a first cut feature disposed on the dielectric layer; 
 a first gate structure disposed on the first fin; and 
 a second gate structure disposed on the second fin, such that the first gate structure and the second gate structure are separated by the first cut feature, 
 wherein the first cut feature comprises an inner layer and an outer layer, the outer layer is disposed on a top surface and sidewalls of the inner layer. 
 
     
     
       2. The device of  claim 1 , further comprising: a second cut feature disposed on the dielectric layer and adjacent to the first fin, wherein a portion of the first gate structure extends over the second cut feature. 
     
     
       3. The device of  claim 2 , wherein a top surface of the first cut feature is above a top surface of the first gate structure. 
     
     
       4. The device of  claim 2 , wherein a thickness of the first cut feature is different from a thickness of the second cut feature. 
     
     
       5. The device of  claim 2 , wherein a composition of a lower portion of the first cut feature is same as a composition of the second cut feature. 
     
     
       6. The device of  claim 1 , wherein the first cut feature further includes an upper layer disposed over the inner layer and the outer layer. 
     
     
       7. The device of  claim 1 , further comprising:
 a third cut feature disposed on the dielectric layer and adjacent to the second fin, 
 wherein a width of the third cut feature is different from a width of the first cut feature. 
 
     
     
       8. The device of  claim 7 , wherein a lower portion of the first cut feature extends into the dielectric layer such that the lower portion of the first cut feature is spaced apart from the first fin and the second fin by the dielectric layer. 
     
     
       9. A device comprising:
 a first fin structure over a substrate; 
 a first cut feature adjacent to the first fin structure and having a first top surface; 
 a first gate structure comprising a first portion disposed directly over the first fin structure and a second portion disposed directly over and in direct contact with the first top surface of the first cut feature; 
 a second fin structure over the substrate; 
 a second cut feature disposed between the first fin structure and the second fin structure and having a second top surface above the first top surface; and 
 a second gate structure over the second fin structure, wherein the second gate structure is electrically isolated from the first gate structure by the second cut feature. 
 
     
     
       10. The device of  claim 9 , further comprising:
 a hard mask layer over the first fin structure, wherein the first gate structure is disposed over the hard mask layer. 
 
     
     
       11. The device of  claim 10 , further comprising:
 an interfacial layer disposed between the first gate structure and sidewalls of the first fin structure, 
 wherein the first gate structure is in direct contact with the hard mask layer. 
 
     
     
       12. The device of  claim 9 , wherein the second cut feature rises above a top surface of the second gate structure. 
     
     
       13. The device of  claim 9 ,
 wherein each of the first cut feature and the second cut feature comprises an inner layer and an outer layer, 
 wherein the outer layer is disposed on a top surface and sidewalls of the inner layer. 
 
     
     
       14. The device of  claim 13 , wherein a composition of the inner layer is different from a composition of the outer layer. 
     
     
       15. The device of  claim 14 , wherein the second cut feature further comprises a dielectric layer disposed on a top surface of the outer layer, and the dielectric layer rises above a top surface of the second gate structure. 
     
     
       16. The device of  claim 9 , wherein a central line of a bottom portion of the second cut feature is offset from a central line of a top portion of the second cut feature. 
     
     
       17. The device of  claim 9 , wherein the first cut feature is an integral structure and is formed of a first material, the second cut feature comprises a first portion formed of the first material and a second portion formed of a second material different from the first material. 
     
     
       18. A semiconductor structure, comprising:
 a substrate; 
 a first fin and a second fin extending from the substrate; 
 a dielectric layer on the substrate and extending between the first fin and the second fin; 
 a first cut feature disposed between the first fin and the second fin, wherein a portion of the first cut feature extends into the dielectric layer and spaced apart from the first fin and the second fin by the dielectric layer, wherein the first cut feature includes a first layer formed of a first material and a second layer formed of a second material and disposed over the first layer, wherein the second material is different from the first material, and a width of the second layer is less than a width of the first layer; 
 a first gate structure disposed over the first fin; and 
 a second gate structure disposed over the second fin and electrically isolated from the first gate structure by the first cut feature. 
 
     
     
       19. The semiconductor structure of  claim 18 , further comprising:
 a second cut feature adjacent to the first fin, 
 wherein the first gate structure is further disposed over the second cut feature, 
 wherein a composition of the second cut feature is different from a composition of the first cut feature. 
 
     
     
       20. The semiconductor structure of  claim 18 , further comprising:
 another dielectric layer over the first gate structure, the second gate structure, and the first cut feature, 
 wherein a portion of the first cut feature extends into the another dielectric layer.