High electron mobility transistor and method for fabricating the same

Abstract

A method for fabricating high electron mobility transistor (HEMT) includes the steps of: forming a buffer layer on a substrate; forming a first barrier layer on the buffer layer, forming a second barrier layer on the first barrier layer, forming a first hard mask on the second barrier layer, removing the first hard mask and the second barrier layer to form a recess; and forming a p-type semiconductor layer in the recess.

What is claimed is: 
     
       1. A method for fabricating a high electron mobility transistor (HEMT), comprising:
 forming a buffer layer on a substrate; 
 forming a first barrier layer on the buffer layer; 
 forming a second barrier layer on the first barrier layer; 
 forming a first hard mask on the second barrier layer; 
 forming a second hard mask on the first hard mask, wherein the first hard mask and the second hard mask comprise different materials; 
 patterning the second hard mask, the first hard mask, the second barrier layer, the first barrier layer, and the buffer layer; 
 forming a third hard mask on a top surface and sidewalls of the patterned second hard mask; 
 removing the patterned first hard mask and the patterned second barrier layer to form a recess; 
 forming a p-type semiconductor layer in the recess; and 
 forming a source electrode and a drain electrode adjacent to two sides of the p-type semiconductor layer. 
 
     
     
       2. The method of  claim 1 , further comprising:
 removing the third hard mask, the patterned second hard mask, the patterned first hard mask, and the patterned second barrier layer to form the recess; 
 forming the p-type semiconductor layer in the recess; 
 removing the third hard mask and the patterned second hard mask; 
 forming a passivation layer on the patterned first hard mask; 
 forming a gate electrode on the p-type semiconductor layer; and 
 forming the source electrode and the drain electrode adjacent to two sides of the gate electrode. 
 
     
     
       3. The method of  claim 2 , wherein the second hard mask and the third hard mask comprise same material. 
     
     
       4. The method of  claim 1 , wherein the first barrier layer and the second barrier layer comprise Al x Ga 1-x N. 
     
     
       5. The method of  claim 4 , wherein the first barrier layer and the second barrier layer comprise different concentrations of Al. 
     
     
       6. The method of  claim 4 , wherein a concentration of Al of the first barrier layer is less than a concentration of Al of the second barrier layer. 
     
     
       7. The method of  claim 1 , wherein a thickness of the first barrier layer is less than a thickness of the second barrier layer. 
     
     
       8. The method of  claim 1 , further comprising forming a metal nitride layer on the buffer layer before forming the first barrier layer. 
     
     
       9. The method of  claim 1 , wherein the p-type semiconductor layer comprises p-type gallium nitride (pGaN).