Integrated circuit package and method

Abstract

In an embodiment, a device includes: a first integrated circuit die having a first contact region and a first non-contact region; an encapsulant contacting sides of the first integrated circuit die; a dielectric layer contacting the encapsulant and the first integrated circuit die, the dielectric layer having a first portion over the first contact region, a second portion over the first non-contact region, and a third portion over a portion of the encapsulant; and a metallization pattern including: a first conductive via extending through the first portion of the dielectric layer to contact the first integrated circuit die; and a conductive line extending along the second portion and third portion of the dielectric layer, the conductive line having a straight portion along the second portion of the dielectric layer and a first meandering portion along the third portion of the dielectric layer.

What is claimed is: 
     
       1. A semiconductor device comprising:
 a plurality of integrated circuit dies, each die having a top surface with a contact region populated with die connectors and a non-contact region free of die connectors; 
 an encapsulant material encapsulating sides of the integrated circuit dies; 
 a dielectric layer over the encapsulant material and the integrated circuit dies; 
 a metallization pattern on the dielectric layer, the metallization pattern including:
 conductive vias extending through the dielectric layer to electrically connect with the die connectors; 
 conductive lines interconnecting the conductive vias, wherein the conductive lines comprise:
 straight portions over the encapsulant material between adjacent integrated circuit dies; and 
 meandering portions over the non-contact regions of the integrated circuit dies, the meandering portions configured to absorb mechanical stress and to facilitate electrical connection between widely spaced die connectors; and 
 
 dummy conductive features at least partially around the conductive vias and along the conductive lines. 
 
 
     
     
       2. The semiconductor device of  claim 1 , wherein the dummy conductive features are configured to be electrically connected to at least one of a power terminal or a ground terminal. 
     
     
       3. The semiconductor device of  claim 1 , wherein the dummy conductive features are configured to be floating terminals not electrically connected to input/output terminals. 
     
     
       4. The semiconductor device of  claim 1 , wherein the meandering portions of the conductive lines have a first width, and the straight portions of the conductive lines have a second width greater than the first width. 
     
     
       5. The semiconductor device of  claim 4 , wherein the conductive lines further comprise:
 connecting portions disposed in the contact regions, the connecting portions having a third width greater than the first width and less than the second width, and connecting the meandering portions to the conductive vias. 
 
     
     
       6. The semiconductor device of  claim 1 , further comprising:
 a redistribution structure on a side of the integrated circuit dies opposite the dielectric layer. 
 
     
     
       7. The semiconductor device of  claim 1 , further comprising:
 a through via extending through the encapsulant material; and 
 a conductive via extending through the dielectric layer to contact the through via. 
 
     
     
       8. A method comprising:
 forming a release layer on a carrier substrate; 
 attaching a plurality of integrated circuit dies to the release layer, each die having a contact region with die connectors and a non-contact region devoid of die connectors; 
 encapsulating the integrated circuit dies with an encapsulant material; 
 forming a dielectric layer over the encapsulant material and the integrated circuit dies; 
 forming a metallization pattern on the dielectric layer, the metallization pattern including conductive vias and conductive lines with meandering portions over the non-contact regions and straight portions over the encapsulant material; 
 forming dummy conductive features at least partially around the conductive vias and along the conductive lines; 
 detaching the carrier substrate from the encapsulated integrated circuit dies; and 
 forming a redistribution structure on a side of the integrated circuit dies opposite the dielectric layer. 
 
     
     
       9. The method of  claim 8 , wherein the meandering portions of the conductive lines are configured to act as springs to absorb mechanical stress during thermal cycling. 
     
     
       10. The method of  claim 8 , further comprising forming under bump metallurgies (UBMs) and conductive connectors on the dielectric layer. 
     
     
       11. The method of  claim 8 , wherein the dummy conductive features are configured to be electrically connected to a ground terminal or a power terminal. 
     
     
       12. The method of  claim 8 , wherein the dummy conductive features are configured to be floating terminals not electrically connected to input/output terminals. 
     
     
       13. The method of  claim 8 , wherein the meandering portions of the conductive lines are formed with varying widths across the integrated circuit dies. 
     
     
       14. The method of  claim 8 , further comprising forming a second dielectric layer over the metallization pattern and a second metallization pattern over the second dielectric layer, wherein the second metallization pattern includes straight conductive lines aligned with the straight portions of the metallization pattern. 
     
     
       15. The method of  claim 8 , further comprising forming a package-on-package (PoP) structure by attaching a second package component to the redistribution structure, wherein the second package component includes additional integrated circuit dies and a substrate with metallization layers for interconnection. 
     
     
       16. A semiconductor package structure comprising:
 a plurality of integrated circuit dies, each die having a contact region with die connectors and a non-contact region devoid of die connectors; 
 an encapsulant to encapsulate the plurality of integrated circuit dies; 
 a dielectric layer on the encapsulant and over the integrated circuit dies; 
 a metallization pattern on the dielectric layer, comprising:
 conductive vias extending through the dielectric layer and electrically connected to the die connectors; 
 conductive lines interconnecting the conductive vias, including:
 straight portions over the encapsulant between adjacent integrated circuit dies; and 
 meandering portions over the non-contact regions of the integrated circuit dies; and 
 
 dummy conductive features in proximity to the conductive vias and along the conductive lines. 
 
 
     
     
       17. The semiconductor package structure of  claim 16 , wherein the dummy conductive features are electrically isolated from the conductive lines. 
     
     
       18. The semiconductor package structure of  claim 16 , wherein the meandering portions of the conductive lines are configured with a first width and the straight portions are configured with a second width, the second width being greater than the first width. 
     
     
       19. The semiconductor package structure of  claim 18 , wherein the conductive lines further comprise connecting portions within the contact regions, the connecting portions having a third width that is intermediate between the first width of the meandering portions and the second width of the straight portions. 
     
     
       20. The semiconductor package structure of  claim 16 , wherein the non-contact regions extend from edges of the plurality of integrated circuit dies to the contact regions of the plurality of integrated circuit dies.