US2002142535A1PendingUtilityA1

Modified nitride spacer for solving charge retention issue in floating gate memory cell

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Assignee: TAIWAN SEMICONDUCTOR MFGPriority: May 5, 2000Filed: May 28, 2002Published: Oct 3, 2002
Est. expiryMay 5, 2020(expired)· nominal 20-yr term from priority
Inventors:Ming-Chou HoWen-Ting ChuChang-Song LinChuan-Li ChangHsin-Ming ChenDi-Son Kuo
H10D 64/01354H10D 64/01346H10D 64/681H10D 64/035H10D 30/6891H10D 30/0227
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Claims

Abstract

A modified nitride spacer and making of the same are disclosed. The modified nitride spacer is formed adjacent a high-temperature oxide (HTO) layer which in turn is formed adjacent the sidewalls of a gate electrode. It is shown that the placement of an intervening oxide layer between the sidewalls of the gate electrode and the nitride spacer, in that order only, provides a significant improvement in charge retention in floating gate memory cells. Also, forming of the spacer from pure, undoped oxide only yields the same favorable results.

Claims

exact text as granted — not AI-modified
What is claimed is:  
     
         1 . A method of forming a modified nitride spacer in a floating gate memory cell comprising the steps of: 
 providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined;    forming a gate oxide layer over said substrate;    forming a polysilicon layer doped with a second conductive type of dopant over said gate oxide layer;    patterning said polysilicon layer to form a gate electrode having sidewalls over said gate oxide layer;    performing first ion implant on said substrate using said gate electrode as a mask to form lightly doped source/drain regions;    forming an oxide layer over said gate electrode;    forming a nitride layer over said oxide layer;    etching said silicon nitride layer to form nitride spacers on sidewalls of said gate electrode; and    performing second ion implant on said substrate using said nitride spacers as a mask to complete the forming of said source/drain regions.    
     
     
         2 . The method of  claim 1 , wherein said forming said gate oxide layer is accomplished by thermal growth at a temperature between about 750 to 1000° C.  
     
     
         3 . The method of  claim 1 , wherein said gate oxide layer has a thickness between about 70 to 120 Å.  
     
     
         4 . The method of  claim 1 , wherein said forming said polysilicon layer is accomplished with silicon source SiH 4  using LPCVD at a temperature between about 400 to 800° C.  
     
     
         5 . The method of  claim 1 , wherein said gate electrode has a thickness between about 1500 to 2500 Å.  
     
     
         6 . The method of  claim 1 , wherein said performing said first ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 16  atoms/cm 2  and energy level between about 50 to 100 KeV.  
     
     
         7 . The method of  claim 1 , wherein said oxide layer has a thickness between about 170 to 800 Å.  
     
     
         8 . The method of  claim 1 , wherein said oxide layer comprises high-temperature oxide (HTO) performed at a temperature between about 400 to 800° C.  
     
     
         9 . The method of  claim 1 , wherein said oxide layer comprises Plasma Enhanced PE-oxide.  
     
     
         10 . The method of  claim 1 , wherein said forming said nitride layer is accomplished by reacting dichlorosilane (SiCl 2 H 2 ) with ammonia (NH 3 ) in an LPCVD at temperature range between about 500 to 900° C.  
     
     
         11 . The method of  claim 1 , wherein the thickness of said nitride layer is between about 800 to 2000 Å.  
     
     
         12 . The method of  claim 1 , wherein said etching is accomplished anisotropically.  
     
     
         13 . The method of  claim 1 , wherein said performing said second ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 16  atoms/cm 2  and energy level between about 50 to 100 KeV.  
     
     
         14 . A method of forming a modified nitride spacer in a floating gate memory cell comprising the steps of: 
 providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined;    forming a gate oxide layer over said substrate;    forming a polysilicon layer doped with a second conductive type of dopant over said gate oxide layer;    patterning said polysilicon layer to form a gate electrode having sidewalls over said gate oxide layer;    performing first ion implant on said substrate using said gate electrode as a mask to form lightly doped source/drain regions;    forming an oxide layer over said gate electrode;    etching said oxide layer to form oxide spacers on sidewalls of said gate electrode; and    performing second ion implant on said substrate using said nitride spacers as a mask to complete the forming of said source/drain regions.    
     
     
         15 . The method of  claim 14 , wherein said forming said gate oxide layer is accomplished by thermal growth at a temperature between about 750 to 1000° C.  
     
     
         16 . The method of  claim 14 , wherein said gate oxide layer has a thickness between about 70 to 120 Å.  
     
     
         17 . The method of  claim 14 , wherein said forming said polysilicon layer is accomplished with silicon source SiH 4  using LPCVD at a temperature between about 400 to 800° C.  
     
     
         18 . The method of  claim 14 , wherein said gate electrode has a thickness between about 1500 to 2500 Å.  
     
     
         19 . The method of  claim 14 , wherein said performing said first ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 16  atoms/cm 2  and energy level between about 50 to 100 KeV.  
     
     
         20 . The method of  claim 14 , wherein said oxide layer has a thickness between about 170 to 800 Å.  
     
     
         21 . The method of  claim 14 , wherein said oxide layer comprises high-temperature oxide (HTO) performed at a temperature between about 400 to 800° C.  
     
     
         22 . The method of  claim 14 , wherein said oxide layer comprises Plasma Enhanced PE-oxide.  
     
     
         23 . The method of  claim 14 , wherein said etching is accomplished anisotropically.  
     
     
         24 . The method of  claim 14 , wherein said performing said second ion implant is accomplished with As ions at a dosage level between about 1×10 15  to 1×10 16  atoms/cm 2  and energy level between about 50 to 100 KeV.  
     
     
         25 . A modified nitride spacer in a floating gate memory cell comprising: 
 providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined;    a gate oxide layer formed over said substrate;    a gate electrode having sidewalls formed over said gate oxide layer;    an oxide layer formed adjacent said sidewalls of said gate electrode; and    a nitride spacer formed adjacent said oxide layer formed adjacent said sidewalls of said gate electrode.    
     
     
         26 . The modified nitride spacer of  claim 24 , wherein said gate oxide layer has a thickness between about  70  to  120  A.  
     
     
         27 . The modified nitride spacer of  claim 24 , wherein said gate electrode has a thickness between about 1500 to 2500 Å.  
     
     
         28 . The modified nitride spacer of  claim 24 , wherein said oxide layer comprises high-temperature oxide (HTO) having a thickness between about 170 to 800 Å.  
     
     
         29 . The modified nitride spacer of  claim 24 , wherein said nitride spacer has a thickness between about 800 to 2000 Å.  
     
     
         30 . A pure oxide spacer in a floating gate memory cell comprising: 
 providing a semiconductor substrate doped with a first conductive type dopant and having a plurality of active and field regions defined;    a gate oxide layer formed over said substrate;    a gate electrode having sidewalls formed over said gate oxide layer;    a high-temperature oxide (HTO) spacer formed adjacent said sidewalls of said gate electrode.    
     
     
         31 . The pure oxide spacer of  claim 30 , wherein said gate oxide layer has a thickness between about 70 to 120 Å.  
     
     
         32 . The pure oxide spacer of  claim 30 , wherein said gate electrode has a thickness between about 1500 to 2500 Å.  
     
     
         33 . The pure oxide spacer of  claim 30 , wherein said HTO spacer has a thickness between about 170 to 800 Å.

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