Three-dimensional stacked substrate arrangements

Abstract

Three-dimensional stacked substrate arrangements with reliable bonding and inter-substrate protection.

1 . A method of manufacturing a semiconductor device having: 
 at least two stacked semiconductor substrates;    a plurality of bonded opposing bumps provided on and bonding opposing ones of the at least two stacked semiconductor substrates together with one another, with ones of the bonded opposing bumps providing electrical conduction paths between the opposing ones of the at least two stacked semiconductor substrates;    the method comprising at least one of:    pre-bonding cleaning of opposing bumps immediately preceding a low temperature bonding; pre-bonding deposition of inter-substrate passivation layers; post-bonding deposition of inter-substrate passivation layers; pre-bonding deposition of support layers to mechanically support substrate thinning; post-bonding deposition of support layers to mechanically support substrate thinning; and, deflection of a thinned substrate during re-bonding of opposing bumps.    
   
   
       2 . A method as claimed in  claim 1 , wherein the method comprises at least two of the recited processes.  
   
   
       3 . A method of manufacturing a semiconductor device having: 
 at least two stacked semiconductor substrates;    a plurality of bonded opposing bumps provided on and bonding opposing ones of the at least two stacked semiconductor substrates together, with ones of the bonded opposing bumps providing electrical conduction paths between the opposing ones of the at least two stacked semiconductor substrates;    the method comprising at least one of:    performing an oxide/contaminant cleaning of surfaces of opposing bumps immediately preceding a low temperature bonding operation to bond the opposing bumps to form the plurality of bonded opposing bumps;    performing a pre-bonding deposition of passivation layers onto at least one of: exposed substrate surfaces of at least one substrate which are destined to lie within an inter-substrate spacing of opposing ones of the at least two stacked semiconductor substrates; and, exposed bump surfaces of at least one substrate of opposing ones of the at least two stacked semiconductor substrates;    performing a post-bonding deposition of passivation layers onto at least one of: exposed substrate surfaces of an inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates; and, exposed bump surfaces of the inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates;    performing a pre-bonding deposition of a mechanical support layer onto at least one substrate of opposing ones of the at least two stacked semiconductor substrates;    performing a post-bonding deposition of a mechanical support layer onto exposed substrate surfaces of an inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates; and,    performing multi-staged bonding by performing an initial bonding of opposing bumps of opposing semiconductor substrates, thinning at least one substrate of the opposing semiconductor substrates to facilitate a predetermined degree of substrate flexing, and performing a secondary bonding of the opposing bumps while applying predetermined pressure to force the opposing semiconductor substrates together.    
   
   
       4 . A method as claimed in  claim 3 , wherein the oxide/contaminant cleaning of the surfaces of the opposing bumps is conducted using at least one of an etching, chemical reaction, heating and mechanical cleaning applied to at least the surfaces of the opposing bumps.  
   
   
       5 . A method as claimed in  claim 3 , wherein the low temperature bonding operation is a bonding operation using temperatures <200° C.  
   
   
       6 . A method as claimed in  claim 3 , wherein the pre-bonding deposition of passivation layers is performed by at least one of: gaseous, vapor, chemical and atomic layer deposition (ALD) of a passivating metal layer; gaseous, vapor, chemical, spinning, carrier solvent, painted, sprayed, poured and extruded deposition of a passivating polymer material; and, gaseous, vapor, chemical, spinning, carrier solvent, painted, sprayed, poured and extruded deposition of a passivating seed material layer.  
   
   
       7 . A method as claimed in  claim 3 , comprising performing the pre-bonding deposition of passivation layers onto the exposed substrate surfaces and/or the exposed bump surfaces of both substrates of opposing ones of the at least two stacked semiconductor substrates.  
   
   
       8 . A method as claimed in  claim 3 , wherein the post-bonding deposition of passivation layers is performed by at least one of: gaseous, vapor, chemical and atomic layer deposition (ALD) of a passivating metal layer; gaseous, vapor, chemical, carrier solvent, injected and capillary deposition of a passivating polymer material; and, gaseous, vapor, chemical, carrier solvent and capillary deposition of a passivating seed material layer.  
   
   
       9 . A method as claimed in  claim 3 , comprising performing the post-bonding deposition of passivation layers onto both the exposed substrate surfaces and the exposed bump surfaces of the inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates.  
   
   
       10 . A method as claimed in  claim 3 , wherein the pre-bonding deposition of the mechanical support layer is performed by at least one of: gaseous, vapor, chemical, spinning, carrier solvent, painted, sprayed, poured and extruded deposition of a supportive polymer material.  
   
   
       11 . A method as claimed in  claim 3 , comprising performing the pre-bonding deposition of the mechanical support layer onto both substrates of opposing ones of the at least two stacked semiconductor substrates.  
   
   
       12 . A method as claimed in  claim 3 , wherein the post-bonding deposition of the mechanical support layer is performed by at least one of: gaseous, vapor, chemical, carrier solvent, injected and capillary deposition of the mechanical support layer between opposing ones of the at least two stacked semiconductor substrates .  
   
   
       13 . A method as claimed in  claim 3 , wherein the mechanical support layer substantially fills the inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates.  
   
   
       14 . A method as claimed in  claim 3 , wherein thinning is performed using at least one of etching, ablation, cleaving, grinding and chemical mechanical polishing (CMP).  
   
   
       15 . A method as claimed in  claim 3 , wherein both the initial bonding and secondary bonding are performed using a low temperature bonding operation using temperatures <200° C.  
   
   
       16 . A method as claimed in  claim 3 , wherein thinning is used to thin at least one substrate to a range of 15 μm to 5 μm average thickness.  
   
   
       17 . A semiconductor device comprising: 
 at least two stacked semiconductor substrates;    a plurality of bonded opposing bumps provided on and bonding opposing ones of the at least two stacked semiconductor substrates together with one another, with ones of the bonded opposing bumps to provide electrical conduction paths between the opposing ones of the at least two stacked semiconductor substrates, and where the plurality of bonded opposing bumps are oxide/contaminant cleaned, low-temperature bonded opposing bumps; and,    at least one of:    pre-bonding deposited passivation layers on at least one of: exposed substrate surfaces of at least one substrate within an inter-substrate spacing of opposing ones of the at least two stacked semiconductor substrates; and, exposed bump surfaces of at least one substrate of opposing ones of the at least two stacked semiconductor substrates;    post-bonding deposited passivation layers on at least one of: exposed substrate surfaces of an inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates; and, exposed bump surfaces of the inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates;    a pre-bonding deposited mechanical support layer on at least one substrate of opposing ones of the at least two stacked semiconductor substrates;    a post-bonding deposited mechanical support layer on exposed substrate surfaces of an inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates; and,    at least one thinned substrate having at least one localized substrate deflection at irregularly-sized ones of the bonded opposing bumps.    
   
   
       18 . A device as claimed in  claim 17 , wherein the bonded opposing bumps are at least one of etching, chemical reaction, heating and mechanical cleaned opposing bumps.  
   
   
       19 . A device as claimed in  claim 17 , wherein the low temperature bonded opposing bumps are <200° C. bonded opposing bumps.  
   
   
       20 . A device as claimed in  claim 17 , wherein the pre-bonding deposited passivation layers are at least one of: gaseous, vapor, chemical and atomic layer deposition (ALD) passivation metal layer; gaseous, vapor, chemical, spinning, carrier solvent, painted, sprayed, poured and extruded passivation polymer layer; and, gaseous, vapor, chemical, spinning, carrier solvent, painted, sprayed, poured and extruded passivation seed material layer.  
   
   
       21 . A device as claimed in  claim 17 , comprising the pre-bonding deposited passivation layers on exposed substrate surfaces and/or the exposed bump surfaces of both substrates of opposing ones of the at least two stacked semiconductor substrates.  
   
   
       22 . A device as claimed in  claim 17 , wherein the post-bonding deposited passivation layers are at least one of: gaseous, vapor, chemical and atomic layer deposition (ALD) passivation metal layer; gaseous, vapor, chemical, carrier solvent, injected and capillary passivation polymer material layer; and, gaseous, vapor, chemical, carrier solvent and capillary passivation seed material layer.  
   
   
       23 . A device as claimed in  claim 17 , comprising the post-bonding deposited passivation layers on both the exposed substrate surfaces and the exposed bump surfaces of the inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates.  
   
   
       24 . A device as claimed in  claim 17 , wherein the pre-bonding deposited mechanical support layer is at least one of: gaseous, vapor, chemical, spinning, carrier solvent, painted, sprayed, poured and extruded supportive polymer material layer.  
   
   
       25 . A device as claimed in  claim 17 , comprising the pre-bonding deposited mechanical support layer on both substrates of opposing ones of the at least two stacked semiconductor substrates.  
   
   
       26 . A device as claimed in  claim 17 , wherein the pre-bonding deposited mechanical support layer is at least one of: gaseous, vapor, chemical, carrier solvent, injected and capillary deposited mechanical support layer between opposing ones of the at least two stacked semiconductor substrates.  
   
   
       27 . A device as claimed in  claim 17 , wherein the pre-bonding deposited mechanical support layer substantially fills the inter-substrate spacing between opposing ones of the at least two stacked semiconductor substrates.  
   
   
       28 . A device as claimed in  claim 17 , wherein the at least one thinned substrate is at least one of an etching, ablation, cleaving, grinding and chemical mechanical polishing (CMP) thinned substrate.  
   
   
       29 . A device as claimed in  claim 17 , wherein the at least one thinned substrate has a thinness in a range of 15 μm to 5 μm average thickness.