Method for fabricating metal layer

Abstract

A method for filling a structure using electrochemical deposition includes a barrier layer and a seed layer being deposited on one or more surfaces of the structure. Metal is electrochemically deposited to fill the structure in an electrochemical plating cell, wherein the electroplating surface of the substrate is tilted and rotated during electrochemical deposition.

1 . A method for electrochemical deposition comprising: 
 providing a substrate; and    electrochemically depositing metal onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition of metal onto the substrate.    
   
   
       2 . The method according to  claim 1 , further comprising depositing a barrier layer and a seed layer on the substrate.  
   
   
       3 . The method according to  claim 2 , wherein deposition of the barrier layer is accomplished by sputtering Ta, TaN, TiN or a ternary compound.  
   
   
       4 . The method according to  claim 2 , wherein deposition of the seed layer is accomplished by electrochemical deposition (ECD) of Cu or chemical vapor deposition (CVD) of Cu.  
   
   
       5 . The method according to  claim 1 , wherein the metal is Cu.  
   
   
       6 . The method according to  claim 1 , wherein a tilt angle of the electroplating surface is between 0.5 to 3 degrees.  
   
   
       7 . The method according to  claim 1 , wherein a rotating speed of the electroplating surface is 150-600 rpm.  
   
   
       8 . A method for fabricating integrated circuit devices on a semiconductor substrate with damascene structures using electrochemical deposition comprising: 
 providing a semiconductor substrate having an insulating layer on the substrate;    providing a level of copper metal interconnecting wiring patterned within the insulating layer;    providing a dielectric layer having a trench opening and a via opening to the copper metal interconnecting wiring;    depositing a barrier layer and a copper seed layer over the dielectric layer covering and lining the trench and via openings; and    electrochemically depositing a copper to fill the trench and via openings in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition.    
   
   
       9 . The method according to  claim 8 , wherein deposition of the barrier layer is accomplished by sputtering Ta, TaN, TiN or a ternary compound.  
   
   
       10 . The method according to  claim 8 , wherein deposition of the copper seed layer is accomplished by electrochemical deposition of Cu or chemical vapor deposition of Cu.  
   
   
       11 . The method according to  claim 8 , wherein a tilt angle of the electroplating surface is between 0 to 3 degrees.  
   
   
       12 . The method according to  claim 8 , wherein a rotating speed of the electroplating surface is 150-600 rpm.  
   
   
       13 . A defect-free, metal layer electrochemically deposited on a semiconductor wafer comprising: 
 a semiconductor wafer; and    an electrochemically deposited metal layer on the semiconductor wafer, wherein a density of defects of the metal layer is less than 1 per mm 2 .    
   
   
       14 . The wafer according to  claim 13 , wherein the semiconductor substrate is a monocrystalline silicon wafer.  
   
   
       15 . The wafer according to  claim 13 , wherein the semiconductor substrate comprises a barrier and a seed layer on the semiconductor substrate.  
   
   
       16 . The wafer according to  claim 13 , wherein the metal layer deposited onto the substrate is Cu.  
   
   
       17 . The wafer according to  claim 13 , wherein the wafer is manufactured by providing a substrate; and electrochemically depositing metal onto the substrate in an electrochemical plating cell, wherein an electroplating surface of the substrate is tilted and rotated during electrochemical deposition of metal onto the substrate.  
   
   
       18 . The wafer according to  claim 13 , wherein a number of defects of the metal layer is less than 50.  
   
   
       19 . The wafer according to  claim 13 , wherein the uniformity of the metal layer is approximately between 1-4%.