Method of forming metal/high-k gate stacks with high mobility

Abstract

The present invention provides a gate stack structure that has high mobilites and low interfacial charges as well as semiconductor devices, i.e., metal oxide semiconductor field effect transistors (MOSFETs) that include the same. In the semiconductor devices, the gate stack structure of the present invention is located between the substrate and an overlaying gate conductor. The present invention also provides a method of fabricating the inventive gate stack structure in which a high temperature annealing process (on the order of about 800° C.) is employed. The high temperature anneal used in the present invention provides a gate stack structure that has an interface state density, as measured by charge pumping, of about 8×10 10 charges/cm 2 or less, a peak mobility of about 250 cm 2 /V-s or greater and substantially no mobility degradation at about 6.0×10 12 inversion charges/cm 2 or greater.

1 . A method of forming a gate stack structure having enhanced mobility comprising: 
 providing a stack including an interlayer comprising at least atoms of Si and O and an overlaying high-k gate dielectric; and    annealing said stack at a temperature of about 800° C. or greater so to provide a gate stack structure having an interface state density, as measured by charge pumping, of about 8×10 10  charges/cm 2  or less, a peak mobility of about 250 cm 2 /V-s or greater and substantially no mobility degradation at about 6.0×10 12  inversion charges/cm 2  or greater.    
   
   
       2 . The method of  claim 1  wherein said annealing is conducted in an inert ambient, a forming gas ambient or a combination thereof.  
   
   
       3 . The method of  claim 1  wherein said temperature is about 900° to about 1100° C.  
   
   
       4 . The method of  claim 1  wherein said annealing comprises a first anneal in N 2  at 1000° C. and a forming gas anneal at a temperature of about 450° C.  
   
   
       5 . The method of  claim 1  wherein said providing and annealing step are integrated into a self-aligned MOSFET process.  
   
   
       6 . The method of  claim 1  wherein said providing and annealing step are integrated into a non-self-aligned MOSFET process.