Semiconductor packages having leadframe-based connection arrays

Abstract

Methods of forming a semiconductor assembly are described which include a leadframe with leads having offset portions exposed at an outer surface of a material package to form a grid array. An electrically conductive compound, such as solder, may be disposed or formed on the exposed lead portions to form a grid array such as a ball grid array (“BGA”) or other similar array-type structure of dielectric conductive elements. The leads may have inner bond ends including a contact pad thermocompressively bonded to a bond pad of the semiconductor chip to enable electrical communication therewith and a lead section with increased flexibility to improve the thermocompressive bond. The inner bond ends may also be wirebonded to the bond pads.

1 . A semiconductor device package, comprising: 
 a packaging material;    at least one lead having a first portion extending in a plane within the packaging material and including a second, bent lead portion extending out of the plane to a pad substantially coplanar with a portion of an exterior surface of the packaging material.    
   
   
       2 . The semiconductor device package of  claim 1 , wherein the second, bent lead portion of the at least one lead returns to a third portion of the at least one lead extending in the plane.  
   
   
       3 . The semiconductor device package of  claim 2 , wherein an end of the third portion is exposed through another portion of the exterior surface of the packaging material.  
   
   
       4 . The semiconductor device package of  claim 3 , wherein the end of the third portion is substantially flush with the another portion of the exterior surface of the packaging material.  
   
   
       5 . The semiconductor device package of  claim 1 , wherein the at least one lead is of substantially constant thickness, measured transverse to the plane.  
   
   
       6 . The semiconductor device package of  claim 1 , wherein the at least one lead comprises a plurality of leads, and wherein: 
 a first lead of the plurality extends in a first direction parallel to the plane;    a second lead of the plurality extends in the first direction parallel to the plane, parallel to the first lead and laterally adjacent thereto; and    the first portions of the first lead and the second lead differ in length.    
   
   
       7 . The semiconductor device package of  claim 6 , wherein the first lead and the second lead have ends of the respective first portions thereof terminating within the packaging material along a common line perpendicular to the first direction.  
   
   
       8 . The semiconductor device package of  claim 7 , wherein the second, bent lead portions of the first lead and the second lead return to respective third lead portions extending in the plane.  
   
   
       9 . The semiconductor device package of  claim 7 , further comprising: 
 a semiconductor chip disposed within the packaging material and having an active surface adjacent the first and second leads; and    a plurality of bond pads on the active surface proximate the ends of the first portions of the first and second leads;    wherein a different bond pad of the plurality is coupled to the ends of each of the first portions of the first and second leads.    
   
   
       10 . The semiconductor device package of  claim 9 , wherein the coupling comprises one of wire bonds and thermocompression bonds.  
   
   
       11 . The semiconductor device package of  claim 9 , further comprising discrete conductive elements disposed on at least some of the pads.  
   
   
       12 . The semiconductor device package of  claim 1 , wherein the package comprises an in-prosess package.  
   
   
       13 . A semiconductor device package, comprising: 
 a semiconductor chip having an active surface with a plurality of bond pads disposed thereon proximate a centerline thereof;    a plurality of leads comprising:    a first set of mutually parallel leads adjacent the active surface, extending in a plane thereto and perpendicular to the centerline toward a periphery of the semiconductor chip; and    a second set of mutually parallel leads adjacent the active surface, extending in the plane parallel thereto and perpendicular to the centerline toward an opposing periphery of the semiconductor chip;    each lead of the plurality including a bent lead portion extending out of the plane to a pad having a surface substantially parallel to the plane.    
   
   
       14 . The semiconductor device package of  claim 13 , wherein the bent lead portions of leads of the plurality return to the plane.  
   
   
       15 . The semiconductor device package of  claim 13 , further comprising a packaging material encapsulating at least the active surface of the semiconductor chip, wherein the pad surfaces of the leads of the plurality are exposed through and substantially flush with a portion of an exterior surface of the packaging material.  
   
   
       16 . The semiconductor device package of  claim 15 , wherein the packaging material substantially completely surrounds the semiconductor chip.  
   
   
       17 . The semiconductor device package of  claim 16 , wherein an end of each lead is exposed through another portion of the exterior surface of the packaging material.  
   
   
       18 . The semiconductor device package of  claim 17 , wherein the end of each third portion is substantially flush with the another portion of the exterior surface of the packaging material.  
   
   
       19 . The semiconductor device package of  claim 13 , wherein each lead of the plurality is of substantially constant thickness, measured transverse to the plane.  
   
   
       20 . The semiconductor device package of  claim 13 , wherein the bent portions of adjacent leads of the mutually parallel leads of a group of leads are located at differing distances from the centerline.  
   
   
       21 . The semiconductor device package of  claim 13 , wherein bond pads of the plurality are coupled to ends of the first portions of the first and second leads.  
   
   
       22 . The semiconductor device package of  claim 21 , wherein the coupling comprises one of wire bonds and thermocompression bonds.  
   
   
       23 . The semiconductor device package of  claim 13 , further comprising discrete conductive elements disposed on pad surfaces of leads of the plurality.  
   
   
       24 . The semiconductor device package of  claim 13 , wherein the package comprises an in-process package.