Barrier layer for semiconductor interconnect structure

Abstract

A method for producing a semiconductor-device having an electrical interconnect. The method produces having an improved barrier layer between the interconnect conductor and the dielectric material in which the interconnect recess is formed. A dielectric layer is formed on top of a wafer substrate having at least one contact region. An interconnect for servicing the contact region is fabricated by forming an interconnect recess and then depositing a primary barrier layer of tantalum nitride and subjecting it to a re-sputtering operation. A film layer of tantalum is then deposited and re-sputtered. Following this operation, a seed layer is formed, and then a conductor is used to fill the interconnect recess. Planerizing the surface of the wafer so that further fabrication may be performed may complete the process.

1 . A method for fabricating a semiconductor device, said method comprising the steps of: 
 providing a substrate having a contact region;    depositing a dielectric layer over the substrate;    forming an interconnect recess in the dielectric layer;    depositing a tantalum nitride (TaN) film within the recess;    re-sputtering the TaN film;    depositing a tantalum (Ta) film over the TaN film; and    re-sputtering the Ta film.    
   
   
       2 . The method according to  claim 1 , further comprising the step of forming a seed layer.  
   
   
       3 . The method according to  claim 2 , further comprising the step of filling the interconnect recess with a conductor.  
   
   
       4 . The method according to  claim 3 , further comprising the step of removing any excess conductor material.  
   
   
       5 . The method according to  claim 4 , wherein the excess material is removed by a chemical mechanical polishing (CMP) operation.  
   
   
       6 . The method according to  claim 3 , wherein the conductor and the seed layer are formed of copper material.  
   
   
       7 . The method according to  claim 1 , wherein the interconnect recess is a trench in communication with a via that extends to the contact region.  
   
   
       8 . The method according to  claim 1 , further comprising the step of cleaning the interconnect recess prior to depositing the TaN film.  
   
   
       9 . The method according to  claim 1 , wherein the re-sputtering steps are performed using an argon plasma.  
   
   
       10 . The method according to  claim 9 , wherein the argon plasma is maintained in a saturate condition during the re-sputtering.  
   
   
       11 . A method of forming an interconnect for use as an electrical connection in a semiconductor device, comprising the steps of: 
 providing a dielectric layer;    forming an interconnect recess;    forming a first barrier layer film;    forming a second barrier layer film on the first barrier layer film;    performing a re-sputtering operation subsequent to forming the second barrier layer film;    forming a seed layer; and    forming a layer of conducting material to substantially fill the interconnect recess.    
   
   
       12 . The method of forming an interconnect of  claim 11 , wherein the interconnect recess is a trench-and-via type recess.  
   
   
       13 . The method of forming an interconnect of  claim 11 , wherein the first barrier layer film is formed of a tantalum nitride material.  
   
   
       14 . The method of forming an interconnect of  claim 11 , wherein the second barrier layer film is formed of a tantalum material.  
   
   
       15 . The method of forming an interconnect of  claim 11 , wherein the re-sputtering operation is performed using an argon plasma.  
   
   
       16 . The method of forming an interconnect of  claim 11 , further comprising the step of performing a re-sputtering operation subsequent to forming the first barrier layer film.  
   
   
       17 . The method of forming an interconnect of  claim 11 , wherein the seed layer is formed of the same material as the conducting material used to substantially fill the interconnect recess.  
   
   
       18 . An interconnect for coupling with a contact region on a semiconductor wafer substrate, comprising: 
 a dielectric layer over the substrate, the dielectric layer forming a recess;    a TaN layer formed within the recess;    a Ta layer formed within the recess;    wherein the Ta layer exhibits a grin density less than or equal to approximately 3.5 per 100 nm; and    a conductor formed in the recess over the TaN layer.    
   
   
       19 . The interconnect of  claim 18 , wherein the Ta layer thickness is greater than or equal to approximately 50 Å.  
   
   
       20 . The interconnect of  claim 18 , wherein the TaN layer thickness is within the range of approximately 50 Å to 150 Å, inclusive.  
   
   
       21 . The interconnect of  claim 20 , wherein the TaN layer thickness is approximately 135 Å.  
   
   
       22 . The interconnect according to  claim 18 , wherein the Ta layer is formed over the TaN layer.  
   
   
       23 . The interconnect according to  claim 22 , further comprising a seed layer formed over the Ta layer.  
   
   
       24 . The interconnect according to  claim 22 , wherein the conductor is copper.  
   
   
       25 . The interconnect according to  claim 22 , wherein the TaN layer is formed by depositing a TaN film and then re-sputtering the TaN film.  
   
   
       26 . The interconnect according to  claim 25 , where in the re-sputtering is performed with argon ions (Ar + ).