Methods and systems for inspection of wafers and reticles using designer intent data

Abstract

Methods and systems for inspection of wafers and reticles using designer intent data are provided. One computer-implemented method includes identifying nuisance defects on a wafer based on inspection data produced by inspection of a reticle, which is used to form a pattern on the wafer prior to inspection of the wafer. Another computer-implemented method includes detecting defects on a wafer by analyzing data generated by inspection of the wafer in combination with data representative of a reticle, which includes designations identifying different types of portions of the reticle. An additional computer-implemented method includes determining a property of a manufacturing process used to process a wafer based on defects that alter a characteristic of a device formed on the wafer. Further computer-implemented methods include altering or simulating one or more characteristics of a design of an integrated circuit based on data generated by inspection of a wafer.

1 .- 85 . (canceled)  
   
   
       86 . A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising: 
 generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an indication of a site in at least one layer of the IC that is susceptible to a process fault;    fabricating the at least one layer of the IC on the wafer; and    applying a process monitoring tool to perform a measurement at the site in the at least one layer responsively to the PDP.    
   
   
       87 . The method according to  claim 86 , wherein applying the process monitoring tool comprises measuring a dimension associated with one or more features of the IC at the site.  
   
   
       88 . The method according to  claim 86 , wherein generating the PDP comprises making a determination that the site is critical to a performance rating of the IC, and selecting the site responsively to the determination.  
   
   
       89 . The method according to  claim 86 , and comprising predicting a yield of the fabrication of the IC responsively to the PDP and to the measurement.  
   
   
       90 . A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising: 
 generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a region in at least one layer of the IC that is characterized by a periodic pattern;    fabricating the at least one layer of the IC on the wafer; and    applying a process monitoring tool to perform a measurement in the region of the at least one layer responsively to the periodic pattern.    
   
   
       91 . The method according to  claim 90 , wherein generating the PDP comprises determining an exact period of a repetitive feature in the periodic pattern, and wherein applying the process monitoring tool comprises capturing multiple images of the feature at locations on the wafer that are mutually spaced by the exact period, and comparing each of the images to another of the images or to a reference image.  
   
   
       92 . The method according to  claim 90 , wherein applying the process monitoring tool comprises determining, responsively to the periodic pattern, a sensitivity setting to be applied by the process monitoring tool in detecting defects in the region, wherein different sensitivity settings are applied by the process monitoring tool in different regions of the at least one layer.  
   
   
       93 . A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising: 
 generating a product design profile (PDP) using an electronic design automation (EDA) tool, the PDP comprising an identification of a plurality of regions in at least one layer of the IC and a respective criticality parameter for each of the regions, indicative of a maximum tolerable defect size in each of the regions;    fabricating at least one layer of the IC on the wafer; and    applying a process monitoring tool to perform a measurement in one or more of the regions in at least one layer responsively to the respective criticality parameter.    
   
   
       94 . The method according to  claim 93 , wherein applying the process monitoring tool comprises setting a defect detection threshold in each of the one or more of the regions responsively to the respective criticality parameter.  
   
   
       95 . The method according to  claim 93 , wherein applying the process monitoring tool comprises selecting the one or more of the regions to inspect responsively to the respective criticality parameter.  
   
   
       96 . The method according to  claim 93 , wherein applying the process monitoring tool comprises detecting a defect in one of the regions, and classifying the defect responsively to the criticality parameter.  
   
   
       97 . A method for monitoring fabrication of an integrated circuit (IC) on a semiconductor wafer, comprising: 
 designing a layout of at least one layer of the IC using an electronic design automation (EDA) tool, at least one layer comprising a structure that is amenable to testing;    generating a product design profile (PDP) using the EDA tool, the PDP comprising information regarding the structure;    fabricating at least one layer of the IC on the wafer; and    applying a process monitoring tool to perform a measurement on the structure in at least one layer, responsively the information in the PDP.