Solder bump on a semiconductor substrate

Abstract

A solder bump on a semiconductor substrate is provided. The solder bump has a semiconductor substrate with a top copper pad thereon, a protective layer on the semiconductor substrate and at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad, wherein the inorganic passivation layer has a thinner portion adjacent a top portion of the first opening. The solder bump further has a soft passivation layer on the inorganic passivation layer with a second opening larger than the first opening, an under bump metal layer conformally formed along the first opening and the second opening and a solder bump formed on the under bump metal layer.

1 . A solder bump on a semiconductor substrate, comprising:
 a semiconductor substrate having a top copper pad thereon;   a protective layer on the semiconductor substrate;   at least one inorganic passivation layer overlying the protective layer with a first opening exposing the top copper pad;   a soft passivation layer with a second opening smaller than the first opening covering the inorganic passivation layer and sidewalls of the first opening;   an under bump metal layer conformally formed along the second opening and on the soft passivation layer; and   a solder bump formed on the under bump metal layer.   
     
     
         2 . The solder bump as claimed in  claim 1 , wherein the top copper pad is embedded in a low-k dielectric material with a dielectric constant less than 3.2 and connects to copper wiring interconnects. 
     
     
         3 . The solder bump as claimed in  claim 1 , wherein the protective layer comprises silicon nitride, silicon oxynitride, or silicon carbide. 
     
     
         4 . The solder bump as claimed in  claim 3 , wherein the inorganic passivation layer is a single layer and comprises silicon oxide. 
     
     
         5 . The solder bump as claimed in  claim 1 , wherein the inorganic passivation layer is triple-layered and comprises a first silicon oxide layer, a second silicon oxide layer and a silicon nitride layer sandwiched between the first and the second silicon oxide layers. 
     
     
         6 . The solder bump as claimed in  claim 5 , wherein the soft passivation layer comprises a photosensitive polymer. 
     
     
         7 . The solder bump as claimed in  claim 6 , wherein the photosensitive polymer comprises polyimide. 
     
     
         8 . The solder bump as claimed in  claim 1 , wherein the protective layer comprises silicon oxide. 
     
     
         9 . The solder bump as claimed in  claim 8 , wherein the inorganic passivation layer is a single layer and comprises silicon nitride, silicon oxynitride, or silicon carbide. 
     
     
         10 . The solder bump as claimed in  claim 8 , wherein the inorganic passivation is triple-layered and comprises a first silicon nitride layer, a second silicon nitride layer and a silicon oxide layer sandwiched between the first and the second silicon nitride layers.