Method of forming a nonplanar transistor with sidewall spacers

Abstract

A semiconductor device comprising a semiconductor body having a top surface and a first and second laterally opposite sidewalls as formed on an insulating substrate is claimed. A gate dielectric is formed on the top surface of the semiconductor body and on the first and second laterally opposite sidewalls of the semiconductor body. A gate electrode is then formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the first and second laterally opposite sidewalls of the semiconductor body. The gate electrode comprises a metal film formed directly adjacent to the gate dielectric layer. A pair of source and drain regions are then formed in the semiconductor body on opposite sides of the gate electrode.

1 . A method of forming a transistor comprising:
 forming a gate electrode having a pair of laterally opposite sidewalls, said gate electrode formed over a channel region of a semiconductor body having the top surface and pair of laterally opposite sidewalls;   forming a hard mask on a top surface of said gate electrode;   blanket depositing a spacer dielectric layer over said hard mask and on said pair of laterally opposite sidewalls of said gate electrode and on said sidewalls and top surface of said semiconductor body;   anisotropically etching back said spacer dielectric layer so that said spacer dielectric layer is removed from the top surface of said hard mask and the top surface of said semiconductor body, and continuing said anisotropic etch back until said spacer dielectric layer is removed from the semiconductor body so that a pair of sidewall spacers are formed adjacent to said sidewalls of said gate electrode and adjacent to a portion of said hard mask on said top surface of said gate electrode.   
     
     
         2 . The method of  claim 1  further comprising forming silicon onto the sidewalls and top surface of said semiconductor body adjacent to said sidewall spacers. 
     
     
         3 . The method of  claim 2  further comprising forming silicide on said silicon film formed on the top surface and sidewalls of said semiconductor body. 
     
     
         4 . The method of  claim 3  wherein said silicide is formed by a method comprising:
 blanket depositing a metal film over said sidewall spacers and said hard mask as well as onto said silicon film formed on said sidewalls and top surface of said semiconductor body;   heating said metal film so that said metal film reacts with said silicon film formed on said semiconductor body to form a silicide film adjacent to the sidewalls and above the top surface of said semiconductor body, wherein said metal film does not react with said sidewalls spacers or said hard mask and wherein said sidewall spacers and said hard mask prevent said metal film from reacting with said gate electrode; and   etching away said unreacted metal film from said hard mask and from said sidewall spacers.   
     
     
         5 . A method of forming a semiconductor device comprising:
 forming a gate electrode material over and around a semiconductor body having a top surface and a pair of laterally opposite sidewalls;   forming a hard mask material on said gate electrode material;   patterning said gate electrode material and said hard mask material into a hard mask and a gate electrode wherein the portion of said semiconductor body beneath said gate electrode defines a channel region of said semiconductor body;   forming a pair of sidewall spacers adjacent to said hard mask and said gate electrode, said sidewall spacers having a top surface above the top surface of said gate electrode and below the top surface of said hard mask.   
     
     
         6 . The method of  claim 5  further comprising:
 etching away said gate electrode to expose a gate dielectric layer;   removing said gate dielectric layer with an etchant to expose said channel region of said semiconductor body;   depositing a second gate dielectric layer on said top surface and sidewalls of said channel region of said semiconductor body; and   depositing a second gate electrode material on said second gate dielectric layer.   
     
     
         7 . The method of  claim 6  wherein forming a second gate electrode material on said gate dielectric layer comprises:
 forming a lower film having a midgap work function and an upper metal film.   
     
     
         8 . The method of  claim 5  wherein said semiconductor body has a height less than the thickness of said hard mask. 
     
     
         9 . The method of  claim 8  further comprising forming silicon on the top surface and sidewalls of said semiconductor body adjacent to the outside edges of said sidewall spacers. 
     
     
         10 . The method of  claim 9  further comprising forming silicide on said silicon film formed on the top surface and sidewalls of said semiconductor body. 
     
     
         11 . The method of  claim 5  wherein said gate electrode comprises polysilicon. 
     
     
         12 . The method of  claim 5  wherein said sidewall spacers are formed by a method comprising:
 blanket comprising a conformal dielectric layer over said sidewalls of said gate electrode, and on the top surface of said hard mask, and onto the sidewalls and the top surface of said semiconductor body; and   anisotropically etching back said conformal dielectric layer so that said conformal dielectric layer is removed from the top surface of said hard mask and the top surface of said semiconductor body, and continuing said anisotropic etch back until said conformal dielectric layer is removed from the sidewalls of said semiconductor body.   
     
     
         13 . The method of  claim 6  further comprising:
 forming a dielectric layer over and around said gate electrode and said hard mask;   planarizing said dielectric layer until said hard mask is exposed and said dielectric layer is substantially planar with the top surface of said hard mask to form a planarized dielectric; and   etching away said hard mask to reveal said gate electrode prior to etching away said gate electrode to expose said gate dielectric layer.   
     
     
         14 . The method of  claim 13  further comprising:
 polishing said gate electrode material on said gate dielectric layer until said gate electrode material and said gate dielectric layer are completely removed from the top surface of said dielectric layer to form a gate electrode and a gate dielectric layer, after depositing said second gate electrode material on said second gate dielectric layer.   
     
     
         15 . A method of forming a semiconductor device comprising:
 forming a gate electrode having a pair of laterally opposite sidewalls on a semiconductor body having a top surface and a pair of laterally opposite sidewalls;   forming a hard mask on said gate electrode material;   forming a pair of sidewall spacers adjacent to said hard mask and said gate electrode, said sidewall spacers having a top surface above the top surface of said gate electrode and below the top surface of said hard mask.   
     
     
         16 . The method of  claim 15  wherein said sidewall spacers are formed by a method comprising:
 blanket comprising a conformal dielectric layer over said sidewalls of said gate electrode, and on the top surface of said hard mask, and onto the sidewalls and the top surface of said semiconductor body; and   anisotropically etching back said conformal dielectric layer so that said conformal dielectric layer is removed from the top surface of said hard mask and the top surface of said semiconductor body, and continuing said anisotropic etch back until said conformal dielectric layer is removed from the semiconductor body so that a pair of sidewall spacers are formed adjacent to said sidewalls of said gate electrode and adjacent to a portion of said hard mask on said top surface of said gate electrode.   
     
     
         17 . The method of  claim 15  further comprising:
 etching away said hard mask and said gate electrode to expose a gate dielectric layer;   removing said gate dielectric layer with an etchant to expose a channel region of said semiconductor body;   depositing a second gate dielectric layer on said top surface of said semiconductor body; and   depositing a second gate electrode material on said second gate dielectric layer.