Increasing body dopant uniformity in multi-gate transistor devices

Abstract

Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.

1 - 7 . (canceled) 
     
     
         8 . A method comprising:
 forming a sacrificial gate structure on a multi-gate fin, the multi-gate fin being coupled with a semiconductor substrate;   removing the sacrificial gate structure to expose the multi-gate fin; and   body doping the multi-gate fin after removing the sacrificial gate structure.   
     
     
         9 . A method according to  claim 8  wherein the body doping is performed after removing the sacrificial gate structure to increase body dopant uniformity in the multi-gate fin by avoiding higher temperature operations that increase body dopant segregation. 
     
     
         10 . A method according to  claim 8  wherein the multi-gate fin comprises a first surface, a second surface, and a third surface wherein the first surface and the third surface are substantially parallel to one another and wherein the first surface and the second surface are substantially perpendicular to one another, wherein the body doping comprises an angled implant between about 10 degrees and about 80 degrees relative to the second surface to increase body dopant uniformity in the multi-gate fin. 
     
     
         11 . A method according to  claim 10  wherein the body doping comprises an angled implant between about 40 degrees and about 70 degrees relative to the second surface wherein the body doping is performed such that at least the first surface, the second surface, and the third surface receive the body doping. 
     
     
         12 . A method according to  claim 8  wherein the body doping comprises an n-type dopant for a p-type metal-oxide-semiconductor (PMOS) device or wherein the body doping comprises a p-type dopant for an n-type metal-oxide-semiconductor (NMOS) device. 
     
     
         13 . A method according to  claim 8  wherein forming a sacrificial gate structure on a multi-gate fin comprises depositing a sacrificial gate dielectric to the multi-gate fin and depositing a sacrificial gate electrode comprising polysilicon to the sacrificial gate dielectric, and wherein removing the sacrificial gate structure to expose the multi-gate fin comprises etching to remove the sacrificial gate structure. 
     
     
         14 . A method according to  claim 8  further comprising:
 forming a subsequent gate structure on the multi-gate fin wherein forming a subsequent gate structure comprises depositing a subsequent gate electrode to the multi-gate fin. 
 
     
     
         15 . A system comprising:
 a processor; and   a memory coupled with the processor, wherein the processor or the memory, or combinations thereof, comprise one or more multi-gate transistor devices comprising:
 a semiconductor substrate; 
 a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed; 
 a dielectric material coupled with the source region and the drain region of the multi-gate fin; and 
 the subsequent gate structure coupled to the gate region of the multi-gate fin. 
   
     
     
         16 . A system according to  claim 15  wherein the gate region of the multi-gate fin is body-doped after the sacrificial gate structure is removed to increase body dopant uniformity in the multi-gate fin by avoiding higher temperature operations that increase body dopant segregation. 
     
     
         17 . A system according to  claim 15  wherein the multi-gate fin comprises a first surface, a second surface, and a third surface wherein the first surface and the third surface are substantially parallel to one another and wherein the first surface and the second surface are substantially perpendicular to one another, wherein the gate region of the multi-gate fin is body-doped at an angle between about 10 degrees and about 80 degrees relative to the second surface. 
     
     
         18 . A system according to  claim 17  wherein the first surface, the second surface, and the third surface of the multi-gate fin are body-doped at an angle between about 40 degrees and about 70 degrees relative to the second surface. 
     
     
         19 . A system according to  claim 15  wherein the body-doped gate region of the multi-gate fin comprises an n-type dopant for a p-type metal-oxide-semiconductor (PMOS) device or wherein the body-doped gate region of the multi-gate fin comprises a p-type dopant for an n-type metal-oxide-semiconductor (NMOS) device. 
     
     
         20 . A system according to  claim 15  wherein the subsequent gate structure comprises:
 a subsequent gate dielectric coupled to the gate region of the multi-gate fin; and 
 a subsequent gate electrode coupled to the gate dielectric.