Stackable semiconductor device packages

Abstract

In one embodiment, a semiconductor device package includes: (1) a substrate unit; (2) connecting elements disposed adjacent to a periphery of the substrate unit and extending upwardly from an upper surface of the substrate unit; (3) a semiconductor device disposed adjacent to the upper surface of the substrate unit and electrically connected to the substrate unit; and (4) a package body disposed adjacent to the upper surface of the substrate unit and covering the semiconductor device. A lateral surface of the package body is substantially aligned with a lateral surface of the substrate unit. The package body defines openings that at least partially expose respective ones of the connecting elements. At least one of the connecting elements has a width W C , and at least one of the openings has a width W U adjacent to an upper surface of the package body, such that W U >W C .

1 .- 20 . (canceled) 
     
     
         21 . A semiconductor package, comprising:
 a substrate including an upper surface;   a plurality of connecting elements disposed adjacent to a periphery of the substrate and extending upwardly from the upper surface of the substrate;   a package body disposed adjacent to the upper surface of the substrate; and   a plurality of openings in the package body, the openings at least partially exposing respective ones of the connecting elements, at least one of the openings having a width W U  adjacent to an upper surface of the package body, such that W U  is in the range of about 250 μm to about 650 μm.   
     
     
         22 . The semiconductor package of  claim 21 , wherein at least one of the connecting elements has a height H C , such that H C  is in the range of about 300 μm to about 350 μm prior to reflow. 
     
     
         23 . The semiconductor package of  claim 21 , wherein at least one of the connecting elements has a height H C , such that H C  is in the range of about 200 μm to about 300 μm after reflow. 
     
     
         24 . The semiconductor package of  claim 21 , wherein the package body has a height H P , such that H P  is in the range of about 100 μm to about 600 μm. 
     
     
         25 . The semiconductor package of  claim 24 , wherein W U >H P . 
     
     
         26 . The semiconductor package of  claim 21 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm. 
     
     
         27 . The semiconductor package of  claim 21 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package. 
     
     
         28 . A semiconductor package, comprising:
 a substrate including an upper surface;   a plurality of connecting elements disposed on the upper surface of the substrate;   a package body disposed on the upper surface of the substrate; and   a plurality of conical openings in the package body, the conical openings exposing respective portions of the connecting elements, at least one of the conical openings having a maximum diameter in the range of about 250 μm to about 650 μm.   
     
     
         29 . The semiconductor package of  claim 28 , wherein at least one of the connecting elements has a height H C , such that H C  is in the range of about 300 μm to about 350 μm prior to reflow. 
     
     
         30 . The semiconductor package of  claim 28 , wherein at least one of the connecting elements has a height H C , such that H C  is in the range of about 200 μm to about 300 μm after reflow. 
     
     
         31 . The semiconductor package of  claim 28 , wherein the package body has a height H P , such that H P  is in the range of about 100 μm to about 600 μm. 
     
     
         32 . The semiconductor package of  claim 31 , wherein the maximum diameter of the at least one of the openings is greater than H P . 
     
     
         33 . The semiconductor package of  claim 28 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm. 
     
     
         34 . The semiconductor package of  claim 28 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package. 
     
     
         35 . A semiconductor package, comprising:
 a substrate including an upper surface;   a plurality of connecting elements disposed on the upper surface of the substrate;   a package body disposed on the upper surface of the substrate wherein the package body has a thickness H P ; and   a plurality of openings in the package body, each of the openings exposing a respective portion of the connecting elements, wherein a maximum width of each of the openings is greater than the thickness H.   
     
     
         36 . The semiconductor package of  claim 35 , wherein at least one of the connecting elements has a height that is in the range of about 300 μm to about 350 μm prior to reflow. 
     
     
         37 . The semiconductor package of  claim 35 , wherein at least one of the connecting elements has a height that is in the range of about 200 μm to about 300 μm after reflow. 
     
     
         38 . The semiconductor package of  claim 35 , wherein H P  is in the range of about 100 μm to about 600 μm. 
     
     
         39 . The semiconductor package of  claim 35 , wherein a pitch of the connecting elements is in the range of about 300 μm to about 800 μm. 
     
     
         40 . The semiconductor package of  claim 35 , wherein the connecting elements provide an electrical connection between the substrate and a second package disposed above the package.