Device with self aligned stressor and method of making same

Abstract

A method includes providing a substrate comprising a substrate material, a gate dielectric film above the substrate, and a first spacer adjacent the gate dielectric film. The spacer has a first portion in contact with a surface of the substrate and a second portion in contact with a side of the gate dielectric film. A recess is formed in a region of the substrate adjacent to the spacer. The recess is defined by a first sidewall of the substrate material. At least a portion of the first sidewall underlies at least a portion of the spacer. The substrate material beneath the first portion of the spacer is reflowed, so that a top portion of the first sidewall of the substrate material defining the recess is substantially aligned with a boundary between the gate dielectric film and the spacer. The recess is filled with a stressor material.

What is claimed is: 
     
         1 . A transistor comprising,
 a substrate comprising a substrate material, a gate dielectric film above the substrate, a gate above the gate dielectric film and first and second spacers adjacent to the gate dielectric film, the first spacer having a portion in contact with a first side of the gate dielectric film, the second spacer having a portion in contact with a second side of the gate dielectric film;   a source stressor region and a drain stressor region in the substrate, the source stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the first spacer, the drain stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the second spacer, the source stressor region and drain stressor region each filled with a stressor material that causes a stress in a channel between the source stressor region and drain stressor region, the source stressor region and the drain stressor region each having a curved bottom edge.   
     
     
         2 . The transistor of  claim 1 , wherein the aligned edges of the source and drain stressor regions have straight portions extending deeper into the substrate than a depth of the channel. 
     
     
         3 . The transistor of  claim 1 , wherein the source and drain stressor regions are U shaped. 
     
     
         4 . The transistor of  claim 1 , wherein the transistor is a PMOS transistor, and the stressor material is SiGe. 
     
     
         5 . The transistor of  claim 1 , wherein the transistor is an NMOS transistor, and the stressor material is SiC. 
     
     
         6 . The transistor of  claim 1 , wherein the substantially aligned edges are in line with the boundaries between the gate dielectric film and the first and second spacers. 
     
     
         7 . The transistor of  claim 1 , wherein:
 the first spacer has an L-shape comprising a first horizontal portion, and   the first horizontal portion and the portion in contact with the first side of the gate dielectric film are made of the same material as each other.   
     
     
         8 . The transistor of  claim 7 , wherein the first horizontal portion has a horizontal length substantially greater than a thickness of the first spacer, the first horizontal portion extending away from the gate dielectric film beyond a side edge of the portion in contact with the first side of the gate dielectric film opposite the gate dielectric film. 
     
     
         9 . The transistor of  claim 8 , wherein the source stressor region has a flat top surface contacting an entire bottom surface of the first horizontal portion. 
     
     
         10 . The transistor of  claim 8 , wherein the flat top surface of the stressor material extends from the first sidewall of the substrate material to an isolation region, and the first horizontal portion of the spacer extends only partially between the first vertical portion and the isolation region. 
     
     
         11 . The transistor of  claim 7 , wherein the substrate material is absent from substantially the entire bottom surface of the horizontal first portion of the first spacer. 
     
     
         12 . The transistor of  claim 1 , wherein a first bond between the gate dielectric film and the substrate material is a covalent bond. 
     
     
         13 . A device comprising,
 a semiconductor substrate;   a gate dielectric film above the substrate;   a gate above the gate dielectric film;   a first L-shaped spacer adjacent to the gate dielectric film, the first L-shaped spacer having a vertical portion in contact with a first side of the gate dielectric film and a horizontal portion extending away from the gate dielectric film beyond a side edge of the vertical portion opposite the gate dielectric film;   a drain stressor region in the substrate, the drain stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the first L-shaped spacer, the drain stressor region filled with a stressor material that causes a stress in a channel adjacent the drain stressor region, the drain stressor material having a flat top surface contacting an entire bottom surface of the horizontal portion.   
     
     
         14 . The device of  claim 13 , wherein the vertical portion and the horizontal portion are made of the same material as each other. 
     
     
         15 . The device of  claim 13 , wherein the flat top surface of the stressor material extends from a sidewall of the substrate material contacting the edge of the drain stressor region to an isolation region, and the horizontal portion of the spacer extends only partially between the vertical portion and the isolation region. 
     
     
         16 . The device of  claim 13 , wherein the aligned edge of the drain stressor region has a straight portion extending deeper into the substrate than a depth of the channel. 
     
     
         17 . The device of  claim 13 , wherein the drain stressor region has a curved bottom edge. 
     
     
         18 . The device of  claim 13 , wherein:
 the aligned edge of the drain region has a straight portion extending deeper into the substrate than a depth of the channel;   the first horizontal portion and the first vertical portion are made of the same material as each other;   the first horizontal portion has a horizontal length substantially greater than a thickness of the first spacer;   a bond between the gate dielectric film and the substrate material is a covalent bond;   the substrate material is absent from substantially the entire bottom surface of the first horizontal portion of the first spacer; and   the flat top surface of the stressor material extends from the first sidewall of the substrate material to an isolation region, and the first horizontal portion of the spacer extends only partially between the first vertical portion and the isolation region.   
     
     
         19 . A device comprising,
 a semiconductor substrate;   a gate dielectric film above the substrate;   a gate above the gate dielectric film;   a first L-shaped spacer and a second L-shaped spacer adjacent to the gate dielectric film, the first L-shaped spacer having a first vertical portion in contact with a first side of the gate dielectric film and a first horizontal portion extending away from the gate dielectric film beyond a side edge of the first vertical portion thereof opposite the gate dielectric film, the second L-shaped spacer having a second vertical portion in contact with a second side of the gate dielectric film and a second horizontal portion extending away from the gate dielectric film beyond a side edge of the second vertical portion thereof opposite the gate dielectric film;   a source stressor region and a drain stressor region in the substrate, the source stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the first L-shaped spacer, the drain stressor region having an edge substantially aligned with a boundary between the gate dielectric film and the second L-shaped spacer, the source stressor region and the drain stressor region filled with a stressor material that causes a stress in a channel between the source stressor region and drain stressor region, the source stressor material having a flat top surface contacting an entire bottom surface of the horizontal portion of the first L-shaped spacer, the drain stressor material having a flat top surface contacting an entire bottom surface of the horizontal portion of the second L-shaped spacer.   
     
     
         20 . The device of  claim 19 , wherein:
 the source stressor region and the drain stressor region each have a curved bottom edge;   the aligned edges of the source and drain regions have straight portions extending deeper into the substrate than a depth of the channel;   the first horizontal portion and the first vertical portion are made of the same material as each other;   the first horizontal portion has a horizontal length substantially greater than a thickness of the first spacer;   a bond between the gate dielectric film and the substrate material is a covalent bond;   the substrate material is absent from substantially the entire bottom surface of the first horizontal portion of the first spacer and the second horizontal portion of the second spacer; and   the flat top surface of the stressor material extends from the first sidewall of the substrate material to an isolation region, and the first horizontal portion of the spacer extends only partially between the first vertical portion and the isolation region.